33742 datasheet(45/65 Pages) FREESCALE

45 / 65 page

Analog Integrated Circuit Device Data

Freescale Semiconductor

33742

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

HIGH-SPEED CAN TRANSCEIVER MODES

The MODE bit (D0) controls the state of the CAN interface, TXRX or Sleep mode (Table 22). SC0 bit (D1) defines the slew

rate when the CAN module is in TXRX, and it controls the wake-up option (wake-up enable or disable) when the CAN module is

in Sleep mode.

INPUT/OUTPUT REGISTER (IOR)

Tables 24 through 26 contain the Input/Output Register information. Table 25 provides information about information HS control

in Normal and Standby modes, while Table 26 provides status bit information.

Table 22. CAN High-Speed Transceiver Modes

SC1

SC0

MODE

CAN Mode

(Pass 1.1)

CAN TXRX, Slew Rate 0

CAN TXRX, Slew Rate 1

CAN TXRX, Slew Rate 2

CAN TXRX, Slew Rate 3

CAN Sleep and CAN Wake-Up Disable

CAN Sleep and CAN Wake-Up Enable

x = Don’t care.

Table 23. CAN Register Status Bits

Name

Logic

Description

CANWU

No CAN wake-up occurred.

CAN wake-up occurred.

CAN-F

No CAN failure.

CAN failure (55).

CAN-UF

Identified CAN failure (55).

Non-identified CAN failure.

THERM-CUR

No overtemperature or overcurrent on CANH or CANL drivers.

Overtemperature or overcurrent on CANH or CANL drivers.

Notes

55.

Error bits are latched in the CAN register.

Table 24. Input/Output Register

IOR

R/W

$011b

–

HSON

–

V2LOW

HSOT

VSUPLOW

DEBUG

Reset Value

–

Reset Condition

(Write) (56)

–

POR

–

Notes

56.

See Table 13, page 42, for definitions of reset conditions.

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