AD9910SLASHPCBZ datasheet(7/60 Pages) AD

7 / 60 page

AD9910

Rev. 0 | Page 7 of 60

Parameter

Conditions/Comments

Min

Typ

Max

Unit

CMOS LOGIC INPUTS

Logic 1 Voltage

2.0

Logic 0 Voltage

0.8

Logic 1 Current

120

μA

Logic 0 Current

μA

Input Capacitance

CMOS LOGIC OUTPUTS

1 mA load

Logic 1 Voltage

2.8

Logic 0 Voltage

0.4

POWER SUPPLY CURRENT

IAVDD (1.8 V)

110

IAVDD (3.3 V)

IDVDD (1.8 V)

222

IDVDD (3.3 V)

TOTAL POWER CONSUMPTION

Single Tone Mode

715

850

Rapid Power-Down Mode

330

400

Full Sleep Mode

1 The gain value for VCO range Setting 5 is measured at 1000 MHz.

2 Wake-up time refers to the recovery from analog power-down. The longest time required is for the Reference Clock Multiplier PLL to relock to the reference. The wake-

up time assumes there is no capacitor on DAC_BP and that the recommended PLL loop filter values are used.

3 SYSCLK cycle refers to the actual clock frequency used on-chip by the DDS. If the reference clock multiplier is used to multiply the external reference clock frequency,

the SYSCLK frequency is the external frequency multiplied by the reference clock multiplication factor. If the reference clock multiplier is not used, the SYSCLK

frequency is the same as the external reference clock frequency.

AD9910/PCBZ Scheda tecnica(PDF) 7 Page - Analog Devices

AD9910/PCBZ Scheda tecnica(HTML) 7 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Scheda tecnica Scarica

Link URL