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SPSB100 Scheda tecnica(PDF) 129 Page - STMicroelectronics

Il numero della parte SPSB100
Spiegazioni elettronici  Automotive power management IC for highly integrated processors
PDF  214 Pages
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Produttore elettronici  STMICROELECTRONICS [STMicroelectronics]
Homepage  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

SPSB100 Scheda tecnica(HTML) 129 Page - STMicroelectronics

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Bit
Name
Description
1: PULL-UP
0: PULL-DOWN
8
WU_CONFIG
Configuration of input pin WU input configured as wake-up input
1: WU configured for input voltage measurement
0: WU configured as wake-up input (default)
Table 87. DCR5 (0x05) LSB
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1 (R/W)
0 (R/W)
0 (R/W)
0 (R/W)
0 (R/W)
0 (R/W)
0 (R/W)
0 (R/W)
WU_ENA
WU_PU
WU_FILT
TIMER_ENA
CRC3
CRC2
CRC1
CRC0
Wake-up
enable bit
Wake-up pull-
up/down
configuration
bit
Wake-up filter
configuration
bit
Timer enable
bit
Cyclic
redundancy
checking bit 3
Cyclic
redundancy
checking bit 2
Cyclic
redundancy
checking bit 1
Cyclic
redundancy
checking bit 0
Table 88. DCR5 (0x05) LSB description
Bit
Name
Description
7
WU_ENA
WU input enable:
1: Device wake-up capability by WU pin enabled (default)
0: No wake-up possible by WU pin
6
WU_PU
WU pull-up/down configuration
1: PULL-UP
0: PULL-DOWN
5
WU_FILT
WU filter configuration bits
1: WU input monitored in cyclic mode with Timer1 (filter time: tWU_cyc, blanking time 80% of timer ON
time)
0: WU input monitored in static mode (filter time tWU_stat) (default)
4
TIMER_ENA
Enables timer counting
1: Allow counting
0: Counter stopped
3
CRC 3
2
CRC 2
1
CRC 1
0
CRC 0
Table 89. DCR6 (0x06) MSB
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
- (R0)
0 (R/W)
0 (R/W)
0 (R/W)
0 (R/W)
0 (R/W)
0 (R/W)
0 (R/W)
RES
MASK_BUCK3_PG_TIMEOUT_IRQ
MASK_BUCK3_OC_IRQ
MASK_BUCK3_PG_IRQ
MASK_BUCK3_IRQ
MASK_BUCK2_PG_TIMEOUT_IRQ
MASK_BUCK2_OC_IRQ
MASK_BUCK2_PG_IRQ
Reserved
Mask BUCK3 PG timeout interrupt bit
Mask BUCK3 over current
interrupt bit
Mask BUCK3 PG interrupt bit
Mask BUCK3 interrupt
bit
Mask BUCK2 PG timeout interrupt bit
Mask BUCK2 over current
interrupt bit
Mask BUCK2 PG interrupt bit
Table 90. DCR6 (0x06) MSB description
Bit
Name
Description
23
RES
Reserved
SPSB100
SPI registers
DS14640 - Rev 1
page 129/214



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