TDA8764ATSSLASH6 datasheet(10/24 Pages) PHILIPS

10 / 24 page

2000 Jul 03

Philips Semiconductors

Product speciﬁcation

10-bit high-speed low-power ADC

TDA8764A

Notes

The rise and fall times of the clock signal must not be less than 0.5 ns.

2. The input admittance is

3. Analog input voltages producing code 0 up to and including code 1023:

a) Voffset(B) (offset voltage BOTTOM) is the difference between the analog input which produces data equal to 00

and the reference voltage BOTTOM (VRB) at Tamb =25 °C.

b) Voffset(T) (offset voltage TOP) is the difference between VRT (reference voltage TOP) and the analog input which

produces data outputs equal to code 1023 at Tamb =25 °C.

4. In order to ensure the optimum linearity performance of such converter architecture the lower and upper extremities

of the converter reference resistor ladder (corresponding to output codes 0 and 1023 respectively) are connected to

pins VRB and VRT via offset resistors ROB and ROT as shown in Fig.4.

a) The current flowing into the resistor ladder is

and the full-scale input range at the converter,

to cover code 0 to 1023, is

b) Since RL, ROB and ROT have similar behaviour with respect to process and temperature variation, the ratio

will be kept reasonably constant from device to device. Consequently variation of the output

codes at a given input voltage depends mainly on the difference VRT − VRB and its variation with temperature and

supply voltage. When several ADCs are connected in parallel and fed with the same reference source, the

matching between each of them is then optimized.

6. The analog bandwidth is defined as the maximum input sine wave frequency which can be applied to the device.

No glitches greater than 2 LSBs, nor any significant attenuation are observed in the reconstructed signal.

Timing (fclk = 60 MHz; CL = 10 pF); see Fig.5 and note 10

tds

sampling delay time

−

0.7

output hold time

−−

output delay time TDA8764ATS

VCCO = 2.7 V

−

VCCO = 3.3 V

−

913

output delay time TDA8764AHL

VCCO = 2.7 V

−

VCCO = 3.3 V

−

digital output load capacitance

−−

slew rate

VCCO = 2.7 V

0.2

0.3

−

V/ns

3-state output delay times (fclk = 60 MHz); see Fig.6

tdZH

enable HIGH

VCCO = 3.3 V

−

tdZL

enable LOW

VCCO = 3.3 V

−

tdHZ

disable HIGH

VCCO = 3.3 V

−

tdLZ

disable LOW

VCCO = 3.3 V

−

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

-----

ωCi

–

------------------------------------------

(

RB )

–

˙ 8375

(

RB )

–

------------------------------------------

1023

–

() V

i(p-p)

–

i(p-p)

----------------------------------------------------

100

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