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DS1372 Scheda tecnica(PDF) 4 Page - Maxim Integrated Products

Il numero della parte DS1372
Spiegazioni elettronici  I2C, 32-Bit, Binary Counter Clock with 64-Bit ID
PDF  12 Pages
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Produttore elettronici  MAXIM [Maxim Integrated Products]
Homepage  https://www.maximintegrated.com/en.html
Logo MAXIM - Maxim Integrated Products

DS1372 Scheda tecnica(HTML) 4 Page - Maxim Integrated Products

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_______________________________________________________________________________________
Pin Description
PIN
NAME
FUNCTION
1, 2
X1, X2
Connections for Standard 32.768kHz Quartz Crystal. The internal oscillator circuitry is designed for
operation with a crystal having a 12.5pF specified load capacitance (CL). Pin X1 is the input to the
oscillator and can optionally be connected to an external 32.768kHz oscillator. The output of the
internal oscillator, pin X2, is floated if an external oscillator is connected to pin X1.
3
AD0
Slave Address Input. This pin is the slave address input for the I2C serial interface and is used to
access multiple devices on the same bus. To select the device, the address value on the pin
must match the corresponding bit in the device addresses. This pin can be connected to VCC or
ground or be driven to a logic-high or logic-low level.
4
GND
Ground
5
SDA
Serial Data Input/Output. This pin is the data input/output for the I2C serial interface. The SDA pin is
open drain and requires an external pullup resistor.
6
SCL
Serial Clock Input. This pin is the clock input for the I2C serial interface and is used to synchronize
data movement on the serial interface.
7
SQW/
INT
Square Wave or Active-Low Interrupt Open-Drain Output. This pin is used to output the square wave
or alarm interrupt signal. The function of this pin is selected by the state of the INTCN control bit.
This pin is open drain and requires an external pullup resistor.
8
VCC
DC Power Pin. This pin should be decoupled using a 0.1μF or 1.0μF capacitor.
DS1372
OSCILLATOR
POWER
÷4096
÷4096
1Hz
1Hz
CLR
4096Hz
8192Hz
32,768Hz
DIVIDER CHAIN
RS[2:1]
X1
SQW/INT
VCC
GND
SDA
SCL
AD0
X2
I2C
INTERFACE
CONTROL/
STATUS
32-BIT
COUNTER
24-BIT ALARM
COUNTER
64-BIT ID
ROM
÷2
÷4
MUX
INTCN
SQW
ACE
AF
MUX
N
Figure 1. Block Diagram
I2C, 32-Bit, Binary Counter Clock with 64-Bit ID



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