4559 datasheet(45/148 Pages) RENESAS

45 / 148 page

Rev.1.04

Aug 23, 2007

Page 45 of 146

REJ03B0188-0104

4559 Group

(4) LCD drive waveform

When “1” is written to a bit in the LCD RAM data, the voltage

difference between common pin and segment pin which

correspond to the bit automatically becomes lVLC3l and the

display pixel at the cross section turns on.

When returning from reset, and in the RAM back-up mode, a

display pixel turns off because every segment output pin and

common output pin becomes VLC3 level.

Fig 46. LCD controller/driver structure

1/2 Duty, 1/2 Bias: When writing (XX10)2 to address M (1, 2, 8) in RAM.

VLC3

VSS

VLC1=VLC2

VLC3

VSS

VLC1=VLC2

(2/F)

1 flame (3/F)

(4/F)

OFF

Voltage level

VLC3

VLC2

VSS

VLC1

VLC3

VLC2

VSS

VLC1

Voltage level

VLC3

VLC2

VSS

VLC1

VLC3

VLC2

VSS

VLC1

Voltage level

COM0

COM1

COM2

COM3

COM1

COM2

COM3

COM2

COM1

COM0

COM1

COM0

COM1

SEG16

COM2

SEG16

COM3

SEG16

COM2

SEG16

COM1

SEG16

COM0

SEG16

COM1

SEG16

COM0

SEG16

COM0

SEG16

M (1, 2, 8)

(bit 0)

M (1, 2, 8)

(bit 0)

M (1, 2, 8)

(bit 0)

(bit 3)

OFF

F : LCD clock frequency

X: Set an arbitrary value.

(These bits are not related to

set the drive waveform at each duty.)

1/F

1/3 Duty, 1/3 Bias: When writing (X101)2 to address M (1, 2, 8) in RAM.

1/4 Duty, 1/3 Bias: When writing (1010)2 to address M (1, 2, 8) in RAM.

1 flame

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