MFS2301BMBACEP datasheet(78/230 Pages) NXP

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NXP Semiconductors

FS23

Safety system basis chip (SBC) with power management, CAN FD and LIN transceivers

WDW_PERIOD[3:0]

Watchdog window period

0000

Disable (infinite open window)

0001

1 ms

0010

2 ms

0011

3 ms

0100

4 ms

0101

6 ms

0110

8 ms

0111

12 ms

1000

16 ms

1001

24 ms

1010

32 ms

0011

64 ms

1100

128 ms

1101 (default)

256 ms

1110

512 ms

1111

1024 ms

Table 34. Watchdog window period configuration

19.2.1 Watchdog selection

Two types of watchdog monitoring, timeout and window watchdog, are implemented and can be selected and

changed during operation by SPI/I2C using WDW_EN bit.

WDW_EN

Watchdog type selection

Timeout watchdog (default)

Window watchdog

Table 35. Watchdog type configuration

19.2.1.1 Timeout watchdog

The timeout watchdog is the default configuration at startup. In this mode, the watchdog period is considered

as fully open, and the MCU writes the correct value in the WD_ANSWER register before the period ends. If

the answer is wrong, or if the answer is not sent before the watchdog timer overflows, the WD error counter is

incremented and WD_NOK_I flag is set to 1.

19.2.1.2 Window watchdog

The window watchdog can be enabled by SPI/I2C by setting WDW_EN bit at 1. In this mode, the watchdog

period is divided in two. The first half is said to be “closed” and the second is said “open”. The MCU writes the

correct value in the WD_ANSWER register during the "open "window. If the answer is wrong, or if the answer is

sent during the "closed" window, or if the answer is not sent before the watchdog timer overflows, the WD error

counter is incremented and WD_NOK_I flag is set to 1.

FS23

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 7.0 — 16 October 2024

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