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ICSSSTUB32866B Scheda tecnica(PDF) 21 Page - Integrated Circuit Systems

Il numero della parte ICSSSTUB32866B
Spiegazioni elettronici  25-Bit Configurable Registered Buffer for DDR2
PDF  28 Pages
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Produttore elettronici  ICST [Integrated Circuit Systems]
Homepage  http://www.icst.com
Logo ICST - Integrated Circuit Systems

ICSSSTUB32866B Scheda tecnica(HTML) 21 Page - Integrated Circuit Systems

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ICSSSTUB32866B
Advance Information
1165—10/25/06
Output Buffer Characteristics
Output edge rates over recommended operating free-air temperature range (See figure 7)
MIN
MAX
dV/dt_r
1
4
V/ns
dV/dt_f
1
4
V/ns
dV/dt_
Δ1
1V/ns
1. Difference between dV/dt_r (rising edge rate) and dV/dt_f (falling edge rate)
PARAMETER
VDD = 1.8V ± 0.1V
UNIT
Electrical Characteristics - DC
TA = 0 - 70°C; VDD = 1.8 +/-0.1V (unless otherwise stated)
SYMBOL
PARAMETERS
VDD
MIN
TYP
MAX
UNITS
VIK
II = -18mA
-1.2
VOH
IOH = -6mA
1.7V
1.2
VOL
IOL = 6mA
1.7V
0.5
II
All Inputs
(2)
VI = VDD or GND
1.9V
-5
5
µA
Standby (Static)
RESET# = GND
100
µA
Operating (Static)
(3)
VI = VIH(AC) or VIL(AC),
RESET# = VDD
40
mA
Dynamic operating
(clock only)
RESET# = VDD,
VI = VIH(AC) or VIL(AC),
CLK and CLK# switching
50% duty cycle.
39
µA/clock
MHz
Dynamic Operating
(per each data input)
1:1 mode
19
Dynamic Operating
(per each data input)
1:2 mode
35
Data Inputs
2.5
3.5
CLK and CLK#
2
3
RESET#
2.5
1.8V
RESET# = VDD,
VI = VIH(AC) or VIL (AC),
CLK and CLK# switching
50% duty cycle. One data
input switching at half
clock frequency, 50%
duty cycle
CONDITIONS
V
µA/ clock
MHz/data
Ci
VI = VREF ±350mV
IDD
IO = 0
1.9V
IDDD
pF
VICR = 1.25V, VI(PP) = 360mV
VI = VDD or GND
Notes:
1 - Guaranteed by design, not 100% tested in production.
2 - PAR_IN leakage current is ±17
μA due to weak pull-down resistor. Allows this device to be used as replacement
for SSTUB32864B (has no parity).
3 - Static operating current will be greater than 40mA if both CLK and CLK# are pulled HIGH or LOW.



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