3

ICSSSTUB32866B

Advance Information

1165—10/25/06

General Description

This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V VDD operation.

All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All

outputs are 1.8-V CMOS drivers that have been optimized to drive the DDR-II DIMM load. ICSSSTUB32866B operates

from a differential clock (CK and CK). Data are registered at the crossing of CK going high, and CK going low.

The C0 input controls the pinout configuration of the 1:2 pinout from A configuration (when low) to B configuration (when

high). The C1 input controls the pinout configuration from 25-bit 1:1 (when low) to 14-bit 1:2 (when high).

Parity that arrives one cycle after the data input to which it applies is checked on the PAR_IN of the first register.

The second register produces to PPO and QERR signals. The QERR of the first register is left floating. The valid

error information is latched on the QERR output of the second register. If an error occurs QERR is latched low for

two cycles or until Reset is low.

B - Single Configuration (CO = 0, C1 = 0)

The device supports low-power standby operation. When the reset input (RST) is low, the differential input receivers

are disabled, and undriven (floating) data, clock and reference voltage (VREF) inputs are allowed. In addition, when

RST is low all registers are reset, and all outputs are forced low. The LVCMOS RST and Cn inputs must always be

held at a valid logic high or low level. To ensure defined outputs from the register before a stable clock has been supplied,

RST must be held in the low state during power up.

In the DDR-II RDIMM application, RST is specified to be completely asynchronous with respect to CK and CK.

Therefore, no timing relationship can be guaranteed between the two. When entering reset, the register will be cleared

and the outputs will be driven low quickly, relative to the time to disable the differential input receivers. However, when

coming out of reset, the register will become active quickly, relative to the time to enable the differential input receivers.

As long as the data inputs are low, and the clock is stable during the time from the low-to-high transition of RST until

the input receivers are fully enabled, the design of the ICSSSTUB32866B must ensure that the outputs will remain

low, thus ensuring no glitches on the output.

The device monitors both DCS and CSR inputs and will gate the Qn outputs from changing states when both DCS and

CSR inputs are high. If either DCS or CSR input is low, the Qn outputs will function normally. The RST input has priority

over the DCS and CSR control and will force the outputs low. If the DCS-control functionality is not desired, then the

CSR input can be hardwired to ground, in which case, the setup-time requirement for DCS would be the same as for

the other D data inputs. Package options include 96-ball LFBGA (MO-205CC).

Parity and Standby Functionality Truth Table

Rst

DCS

CSR

CK

CK

Sum of Inputs = H

(D1 - D25)

PAR_IN

PPO

QERR

HL

X

↑↓

Even

LLH

HL

X

↑↓

Odd

L

H

L

HL

X

↑↓

Even

H

H

L

HL

X

↑↓

Odd

H

L

H

HH

L

↑↓

Even

LLH

HH

L

↑↓

Odd

H

H

L

HH

H

↑↓

XX

H

X

X

L or H

L or H

X

X

L

X or

Floating

X or

Floating

X or

Floating

X or

Floating

X or Floating

X or

Floating

LH

3. PAR_IN arrives two clock cycles after the data to which it applies when CO = 1.

Inputs

Outputs

4. Assume QERR is high at the CK

↑ and CK↓ crossing. If QERR is low it stays latched low for two

clock cycles on until Rst is low.

1. CO = 0 and CI = 0, Data inputs are D2, D3, D5, D6, D8 - D25.

CO = 0 and CI = 1, Data inputs are D2, D3, D5, D6, D8 - D14

CO = 1 and CI = I, Data inputs are D1 - D6, D8 - D10, D12, D13

2. PAR_IN arrives one clock cycle after the data to which it applies when CO = 0.