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AM69 Scheda tecnica(PDF) 67 Page - Texas Instruments |
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AM69 Scheda tecnica(HTML) 67 Page - Texas Instruments |
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67 / 312 page ![]() Table 5-1. Pin Attributes (ALY, AND Packages) (continued) ALY Ball Num [1] AND Ball Num [1] Ball Name [2] PADCFG Register [15] PADCFG Address [16] Signal Name [3] Mux Mode [4] Signal Type [5] I/O Voltage [6] Ball State DURING Reset (RX/TX/PULL) [7] Ball State AFTER Reset (RX/TX/PULL) [8] Mux Mode AFTER Reset [9] Pull Type [10] Power [11] Hys [12] Voltage Buffer Type [13] IO RET [14] AV6 AK11 SERDES1_TX0_N PCIE0_TXN0 O 1.8 V VDDA_0P8_ SERDES0_1 / VDDA_0P8_ SERDES_C0 _1 / VDDA_1P8_ SERDES0_1 4L_PHY SGMII3_TXN0 O AV7 AK12 SERDES1_TX0_P SGMII3_TXP0 O 1.8 V VDDA_0P8_ SERDES0_1 / VDDA_0P8_ SERDES_C0 _1 / VDDA_1P8_ SERDES0_1 4L_PHY PCIE0_TXP0 O AR5 AM9 SERDES1_TX1_N PCIE0_TXN1 O 1.8 V VDDA_0P8_ SERDES0_1 / VDDA_0P8_ SERDES_C0 _1 / VDDA_1P8_ SERDES0_1 4L_PHY SGMII4_TXN0 O AR6 AM10 SERDES1_TX1_P PCIE0_TXP1 O 1.8 V VDDA_0P8_ SERDES0_1 / VDDA_0P8_ SERDES_C0 _1 / VDDA_1P8_ SERDES0_1 4L_PHY SGMII4_TXP0 O AR2 AK8 SERDES1_TX2_N SGMII1_TXN0 O 1.8 V VDDA_0P8_ SERDES0_1 / VDDA_0P8_ SERDES_C0 _1 / VDDA_1P8_ SERDES0_1 4L_PHY PCIE2_TXN0 O PCIE0_TXN2 O AR3 AK9 SERDES1_TX2_P SGMII1_TXP0 O 1.8 V VDDA_0P8_ SERDES0_1 / VDDA_0P8_ SERDES_C0 _1 / VDDA_1P8_ SERDES0_1 4L_PHY PCIE2_TXP0 O PCIE0_TXP2 O www.ti.com AM69A, AM69 SPRSP92C – FEBRUARY 2023 – REVISED JUNE 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 67 Product Folder Links: AM69A AM69 |
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