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AM69 Scheda tecnica(PDF) 93 Page - Texas Instruments

Il numero della parte AM69
Spiegazioni elettronici  AM69x Processors, Silicon Revision 1.0
PDF  312 Pages
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Produttore elettronici  TI [Texas Instruments]
Homepage  http://www.ti.com
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AM69 Scheda tecnica(HTML) 93 Page - Texas Instruments

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Table 5-5. DDRSS0 Signal Descriptions (continued)
SIGNAL NAME [1] ((2))
PIN TYPE [2]
DESCRIPTION [3]
ALY PIN [4]
AND PIN [4]
DDR0_DQ9
IO
DDRSS Data
W3
V7
DDR0_DQ10
IO
DDRSS Data
AA3
W3
DDR0_DQ11
IO
DDRSS Data
W2
V5
DDR0_DQ12
IO
DDRSS Data
AA6
W6
DDR0_DQ13
IO
DDRSS Data
Y4
U2
DDR0_DQ14
IO
DDRSS Data
Y5
W4
DDR0_DQ15
IO
DDRSS Data
AA7
U3
DDR0_DQ16
IO
DDRSS Data
AF2
AD5
DDR0_DQ17
IO
DDRSS Data
AE7
AC3
DDR0_DQ18
IO
DDRSS Data
AG3
AE3
DDR0_DQ19
IO
DDRSS Data
AF5
AB2
DDR0_DQ20
IO
DDRSS Data
AE6
AC4
DDR0_DQ21
IO
DDRSS Data
AF4
AD2
DDR0_DQ22
IO
DDRSS Data
AE3
AC6
DDR0_DQ23
IO
DDRSS Data
AE4
AD4
DDR0_DQ24
IO
DDRSS Data
AG5
AG4
DDR0_DQ25
IO
DDRSS Data
AH3
AG2
DDR0_DQ26
IO
DDRSS Data
AJ2
AF3
DDR0_DQ27
IO
DDRSS Data
AH4
AE5
DDR0_DQ28
IO
DDRSS Data
AJ4
AE6
DDR0_DQ29
IO
DDRSS Data
AH6
AG5
DDR0_DQ30
IO
DDRSS Data
AH7
AF4
DDR0_DQ31
IO
DDRSS Data
AG6
AH6
DDR0_DQS0N
IO
DDRSS Complimentary Data Strobe
V1
T1
DDR0_DQS0P
IO
DDRSS Data Strobe
U1
R1
DDR0_DQS1N
IO
DDRSS Complimentary Data Strobe
Y1
W1
DDR0_DQS1P
IO
DDRSS Data Strobe
AA1
V1
DDR0_DQS2N
IO
DDRSS Complimentary Data Strobe
AE1
AC1
DDR0_DQS2P
IO
DDRSS Data Strobe
AF1
AD1
DDR0_DQS3N
IO
DDRSS Complimentary Data Strobe
AH1
AF1
DDR0_DQS3P
IO
DDRSS Data Strobe
AJ1
AG1
(1)
An external 240 Ω ±1% resistor must be connected between this pin and VSS. No external voltage should be applied to this pin.
(2)
DDRSS0, DDRSS1, DDRSS2, and DDRSS3 must always be used in incremental order. For instance, when using a single LPDDR
component, it must be connected to the DDR0_* interface. When using two LPDDR components, they must be connected to DDR0_*
and DDR1_* interfaces, and so forth.
Table 5-6. DDRSS1 Signal Descriptions
SIGNAL NAME [1] ((2))
PIN TYPE [2]
DESCRIPTION [3]
ALY PIN [4]
AND PIN [4]
DDR1_CKN
IO
DDRSS Differential Clock (negative)
A11
H1
DDR1_CKP
IO
DDRSS Differential Clock (positive)
B10
J2
DDR1_RESETn
IO
DDRSS Reset
G10
G5
DDR1_RET
I
DDR Retention Enable
G8
G8
DDR1_CA0
IO
DDRSS Command Address
F12
J4
DDR1_CA1
IO
DDRSS Command Address
C12
H3
DDR1_CA2
IO
DDRSS Command Address
B12
G2
DDR1_CA3
IO
DDRSS Command Address
C11
J3
www.ti.com
AM69A, AM69
SPRSP92C – FEBRUARY 2023 – REVISED JUNE 2024
Copyright © 2024 Texas Instruments Incorporated
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