RM5261™ Microprocessor with 64-Bit System Bus Data Sheet

Released

Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use

8

Document ID: PMC-2002241, Issue 1

List of Tables

Table 1 Integer Multiply/Divide Operations ................................................................................13

Table 2 Floating-Point Instruction Cycles ..................................................................................14

Table 3 Cache Attributes ...........................................................................................................20

Table 4 Boot-Time Mode Bit Stream .........................................................................................25

Table 5 System Interface ...........................................................................................................26

Table 6 Clock/Control Interface .................................................................................................27

Table 7 Interrupt Interface .........................................................................................................27

Table 8 JTAG Interface .............................................................................................................27

Table 9 Initialization Interface ....................................................................................................28

Table 10 Power Supply .............................................................................................................28

Table 11 DC Electrical Characteristics ......................................................................................31