RM5261 datasheet(16/40 Pages) PMC

16 / 40 page

Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use

Document ID: PMC-2002241, Issue 1

RM5261™ Microprocessor with 64-Bit System Bus Data Sheet

Released

Figure 4

CP0 Registers

3.13 Virtual to Physical Address Mapping

The RM5261 provides three modes of virtual addressing:

•

user mode

•

kernel mode

•

supervisor mode

This mechanism is available to system software to provide a secure environment for user

processes. Bits in the CP0 register Status determine which virtual addressing mode is used. In the

user mode, the RM5261 provides a single, uniform virtual address space of 1TB (2 GB in 32-bit

mode).

When operating in the kernel mode, four distinct virtual address spaces, totalling over 2.5TB (4

GB in 32-bit mode), are simultaneously available and are differentiated by the high-order bits of

the virtual address.

The RM5261 processors also support a supervisor mode in which the virtual address space over

2TB (2.5 GB in 32-bit mode), divided into three regions based on the high-order bits of the virtual

address.

When the RM5261 is configured as a 64-bit microprocessor, the virtual address space layout is an

upward compatible extension of the 32-bit virtual address space layout.

Figure 5 shows the address space layout for 32-bit operation.

TLB

(entries protected

from TLBWR)

EntryHi

10*

EntryLo0

EntryLo1

PageMask

Wired

Random

Index

Status

12*

Cause

13*

EPC

14*

ErrorEPC

30*

Count

Compare

11*

Context

PRId

15*

Config

16*

TagHi

29*

TagLo

28*

ECC

26*

CacheErr

27*

BadVAddr

LLAddr

17*

* Register number

XContext

20*

Used for memory

management

Used for exception

processing

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