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GL800HT25 Scheda tecnica(PDF) 6 Page - GENESYS LOGIC

Il numero della parte GL800HT25
Spiegazioni elettronici  USB 2.0 UTMI Compliant Transceiver IP Core
PDF  20 Pages
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Produttore elettronici  GENESYS [GENESYS LOGIC]
Homepage  http://www.genesyslogic.com
Logo GENESYS - GENESYS LOGIC

GL800HT25 Scheda tecnica(HTML) 6 Page - GENESYS LOGIC

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GL800HT25 USB 2.0 UTMI Compliant Transceiver IP Core
©2000-2003 Genesys Logic Inc.—All rights reserved.
Page 6
CHAPTER 1
GENERAL DESCRIPTION
GL800HT25 is a high performance USB 2.0 Transceiver compliant with the UTMI (USB 2.0 Transceiver
Macrocell Interface) Specification proposed by Intel. The UTMI specification defines a standard interface to
USB 2.0 high-speed transceivers that enables common design across prototype and production
implementations.
The GL800HT25 integrates high-speed, mixed-signal circuitry to serve as the interface between the high
performance USB serial bus and the 16-bit SIE bus. The transceiver is controlled by input signals from the SIE
bus, which is synchronized with the 30MHz clock output. The UTMI transceiver handles the low level USB
protocol and signaling. This includes features such as: data serialization and deserialization, bit stuffing and
clock recovery and synchronization. The primary focus of the UTMI transceiver is to shift the clock domain of
the data from the USB 2.0 rate to one that is compatible with the general logic.
To eliminate the difficult high-speed, mixed-signal USB 2.0 logic design for system and peripheral developers,
the GL800HT25 with standard UTMI and 40X improvement in data rate can be easily adapted for
implementation of USB 2.0 high speed compliant design of widely applications, including scanners, printers,
portable storage, external CD-ROM / CD-RW / DVD-ROM, flash card readers, and PC cameras. The IP block
now is certified and available on the 0.35µm UMC standard CMOS process; and it is also scheduled for
0.25µm TSMC standard CMOS process in 3Q’02.



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