GL800HT25 datasheet(13/20 Pages) GENESYS

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GL800HT25 USB 2.0 UTMI Compliant Transceiver IP Core

Page 13

DMH

Negative USB Differential Data (High Speed)

AGND0~1

11,16

Analog ground (0V)

RREF

510 Ω reference resistor input

Crystal output

12MHz crystal/oscillator input

TEST0

(pd)

Test mode enable

OPMOD1

(pu)

OPMOD0

(pd)

Operational mode. These signals select between various

operational modes:

[1] [0] Description

0: Normal Operation

1: Non-Driving

2: Disable Bit Stuffing and NRZI encoding

3: Reserved

RXACTV

Receive Active, active high. Indicates that the receive state

machine has detected SYNC and is active. RXACTV is negated

after a Bit Stuff Error or an EOP is detected.

In HS mode, RXACTV must be negated no less than 3 and no

more than 8 CLKs after an Idle state is detected on the USB.

And RXACTV must be negated for at least 1 CLK between

consecutive received packets.

In FS/FS only modes, RXACTV must be negated no more than 2

CLKs after a FS Idle state is detected on the USB. And RXACTV

must be negated for at least 4 CLKs between consecutive received

packets.

RXERR

Receive Error, active high.

0: Indicates no error.

1: Indicates that a receive error has been detected.

This output is clocked with the same timing as the Data lines and

can occur at anytime during a transfer. If asserted, it will force the

negation of RXVLD on the next rising edge of CLK30.

RXVLD

Receive Data Valid, active high. Indicates that the Data bus has

valid data. The Rx Register is full and ready to be unloaded. The

SIE is expected to latch the Data bus on the clock edge.

CLKOUT

Clock. This 30MHz clock output is used for clocking receive and

transmit HS/FS 16-bit parallel data.

TXVLD

Transmit Valid, active high. Indicates that the Data bus is valid.

The assertion of Transmit Valid initiates SYNC on the USB. The

negation of Transmit Valid initiates EOP on the USB.

In HS mode, the SYNC pattern must be asserted on the USB

between 8 and 16 bit times after the assertion of TXVLD is

detected by the Transmit State Machine.

In FS/ FS only Modes, the SYNC pattern must be asserted on the

USB no less than 1 CLK and no more than 5 CLKs after the

assertion of TXVLD is detected by the Transmit State Machine.

VALIDH

Transmit/Receive Valid High, active high.

TXRDY

Transmit data ready, active high. If TXVLD is asserted, the SIE

must always have data available for clocking in to the TX Register

on the rising edge of CLK30. If TXVLD is true and TXRDY is

asserted at the rising edge of CLK30, the GL800HT25 will load

the data on the Data bus into the TX Register on the next rising

edge of CLK30, at that time, SIE should immediately present the

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