www.ti.com

Thisisanexampleblockdiagram.

Low-JitterClockDistribution

ADC

ADS5474

VCXO

REF

CDC

(ClockDistributionChip)

CDCM7005

800MHz(totransmitDAC)

100MHz(toDSP)

200MHz(toFPGA)

ToOther

BoardMaster

ReferenceClock

(highorlowjitter)

10MHz

400MHz

Low-JitterOscillator

800MHz

LVPECL

LVPECL

or

LVCMOS

CLKIN

CLKIN

Digital Outputs

ADS5474

SLAS525 – JULY 2007

Consult the CDCM7005 data sheet for proper schematic and specifications regarding allowable input and output

frequency and amplitude ranges.

Figure 48. Acceptable Jitter Clock Circuit

The ADC provides 14 LVDS-compatible, offset binary data outputs (D13 to D0; D13 is the MSB and D0 is the

LSB), a data-ready signal (DRY), and an over-range indicator (OVR). It is recommended to use the DRY signal

to capture the output data of the ADS5474. DRY is source-synchronous to the DATA/OVR outputs and operates

at the same frequency, creating a half-rate DDR interface that updates data on both the rising and falling edges

of DRY. It is recommended that the capacitive loading on the digital outputs be minimized. Higher capacitance

shortens the data-valid timing window. The values given for timing (see Figure 1) were obtained with a

measured 10-pF parasitic board capacitance to ground on each LVDS line (or 5-pF differential parasitic

capacitance). When setting the time relationship between DRY and DATA at the receiving device, it is generally

recommended that setup time be maximized, but this partially depends on the setup and hold times of the

device receiving the digital data (like an FPGA or Field Programmable Field Array). Since DRY and DATA are

coincident, it will likely be necessary to delay either DRY or DATA such that setup time is maximized.

Referencing Figure 1, the polarity of DRY with respect to the sample N data output transition is undetermined

because of the unknown startup logic level of the clock divider that generates the DRY signal (DRY is a

frequency divide-by-two of CLK). Either the rising or the falling edge of DRY will be coincident with sample N

and the polarity of DRY could invert when power is cycled off/on or when the power-down pin is cycled. Data

capture from the transition and not the polarity of DRY is recommended, but not required. If the synchronization

of multiple ADS5474 devices is required, it might be necessary to use a form of the CLKIN signal rather than

DRY to capture the data.

The DRY frequency is identical on the ADS5474 to the ADS5463 (where DRY equals 1/2 CLK frequency), but

different than it is on the pin-similar ADS5444/ADS5440 (where DRY equals the CLK frequency). The LVDS

outputs all require an external 100-

Ω load between each output pair in order to meet the expected LVDS voltage

levels. For long trace lengths, it may be necessary to place a 100-

Ω load on each digital output as close to the

ADS5474 as possible and another 100-

Ω differential load at the end of the LVDS transmission line to provide

matched impedance and avoid signal reflections. The effective load in this case reduces the LVDS voltage

levels by half.

The OVR output equals a logic high when the 14-bit output word attempts to exceed either all 0s or all 1s. This

flag is provided as an indicator that the analog input signal exceeded the full-scale input limit of approximately

signal within acceptable limits.

27

Submit Documentation Feedback