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DSP56303 Scheda tecnica(PDF) 40 Page - Freescale Semiconductor, Inc

Il numero della parte DSP56303
Spiegazioni elettronici  DSP56303 USER?셎 MANUAL
PDF  292 Pages
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Produttore elettronici  FREESCALE [Freescale Semiconductor, Inc]
Homepage  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

DSP56303 Scheda tecnica(HTML) 40 Page - Freescale Semiconductor, Inc

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DSP56303 User’s Manual, Rev. 2
2-16
Freescale Semiconductor
Signals/Connections
2.10 Serial Communication Interface (SCI)
The Serial Communication interface (SCI) provides a full duplex port for serial communication
with other DSPs, microprocessors, or peripherals such as modems.
SCK1
PD3
Input/Output
Input or Output
Input
Disconnected
internally
Serial Clock
Provides the serial bit rate clock for the ESSI interface for both the
transmitter and receiver in Synchronous modes, or the transmitter
only in Asynchronous modes.
Although an external serial clock can be independent of and
asynchronous to the DSP system clock, it must exceed the
minimum clock cycle time of 6 T (that is, the system clock
frequency must be at least three times the external ESSI clock
frequency). The ESSI needs at least three DSP phases inside each
half of the serial clock.
Port D 3
The default configuration following reset is GPIO. For PD3, signal
direction is controlled through PRRD.
This signal is configured as SCK1 or PD3 through PCRD. This
input is 5 V tolerant.
SRD1
PD4
Input
Input or Output
Input
Disconnected
internally
Serial Receive Data
Receives serial data and transfers the data to the ESSI receive
shift register. SRD0 is an input when data is being received.
Port D 4
The default configuration following reset is GPIO. For PD4, signal
direction is controlled through PRRD. This signal is configured as
SRD1 or PD4 through PCRD. This input is 5 V tolerant.
STD1
PD5
Output
Input or Output
Input
Disconnected
internally
Serial Transmit Data
Transmits data from the serial transmit shift register. STD1 is an
output when data is being transmitted.
Port C 5
The default configuration following reset is GPIO. For PD5, signal
direction is controlled through PRRD. This signal is configured as
STD1 or PD5 through PCRD. This input is 5 V tolerant.
Notes: 1.
The Wait processing state does not affect the signal state.
Table 2-13. Enhanced Synchronous Serial Interface 1 (ESSI1) (Continued)
Signal
Name
Type
State During1
Signal Description
Reset
Stop



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