DSP56303 datasheet(113/292 Pages) FREESCALE

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DSP Core Programming Model

DSP56303 User’s Manual, Rev. 2

Freescale Semiconductor

6-13

6.6.2 Host Status Register (HSR)

The HSR is a 16-bit read-only status register by which the DSP reads the HI08 status and flags.

The host processor cannot access it directly. The initialization values for the HSR bits are

discussed in Section 6.6.9, DSP-Side Registers After Reset, on page 6-20.

HCIE

Host Command Interrupt Enable

Generates a host command interrupt request if the host command pending

(HCP) status bit in the HSR is set. If HCIE is cleared, HCP interrupts are

disabled. The interrupt address is determined by the host command vector

NOTE: If more than one interrupt request source is asserted and enabled

(for example, HRDF is set, HCP is set, HRIE is set, and HCIE is set), the

HI08 generates interrupt requests according to priorities shown here. The bit

value is indeterminate after an individual reset.

Priority

Interrupt Source

Highest

Host Command (HCP = 1)

Transmit Data (HTDE = 1)

Lowest

Receive Data (HRDF = 1)

1HTIE

Host Transmit Interrupt Enable

Generates a host transmit data interrupt request if the host transmit data

empty (HTDE) bit in the HSR is set. The HTDE bit is set when data is

transferred from the HTX to the RXH, RXM, or RXL registers. If HTIE is

cleared, HTDE interrupts are disabled. The bit value is indeterminate after

an individual reset.

HRIE

Host Receive Interrupt Enable

Generates a host receive data interrupt request if the host receive data full

(HRDF) bit in the host status register (HSR, Bit 0) is set. The HRDF bit is set

when data is transferred to the HRX from the TXH, TXM, or TXL registers. If

HRIE is cleared, HRDF interrupts are disabled. The bit value is

indeterminate after an individual reset.

9876

54321

HF1

HF0

HCP HTDE HRDF

—Reserved bit; read as 0; write to 0 for future compatibility.

Figure 6-7. Host Status Register (HSR) (X:$FFFFC3)

Table 6-9. Host Status Register (HSR) Bit Definitions

Bit Number

Bit Name

Reset Value

Description

15–5

Reserved. Write to 0 for future compatibility.

Table 6-8. Host Control Register (HCR) Bit Definitions

Bit Number

Bit Name

Reset Value

Description

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