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DSP56303 User’s Manual, Rev. 2

7-6

Freescale Semiconductor

Enhanced Synchronous Serial Interface (ESSI)

7.3 Operation

This section discusses ESSI basics: reset state, initialization, and exceptions.

7.3.1 ESSI After Reset

A hardware RESET signal or software reset instruction clears the port control register and the port

direction control register, thus configuring all the ESSI signals as GPIO. The ESSI is in the reset

state while all ESSI signals are programmed as GPIO; it is active only if at least one of the ESSI

I/O signals is programmed as an ESSI signal.

7.3.2 Initialization

To initialize the ESSI, do the following:

Send a reset: hardware RESET signal, software reset instruction, ESSI individual reset,

or stop instruction reset.

Program the ESSI control and time slot registers.

Write data to all the enabled transmitters.

Configure at least one signal as ESSI signal.

If an external frame sync is used, from the moment the ESSI is activated, at least five (5)

serial clocks are needed before the first external frame sync is supplied. Otherwise,

improper operation may result.

When the PC[5–0] bits in the GPIO Port Control Register (PCR) are cleared during program

execution, the ESSI stops serial activity and enters the individual reset state. All status bits of the

interface are set to their reset state. The contents of CRA and CRB are not affected. The ESSI

individual reset allows a program to reset each interface separately from the other internal

peripherals. During ESSI individual reset, internal DMA accesses to the data registers of the

ESSI are not valid, and data read there are undefined. To ensure proper operation of the ESSI, use

an ESSI individual reset when you change the ESSI control registers (except for bits TEIE, REIE,

TLIE, RLIE, TIE, RIE, TE2, TE1, TE0, and RE).

Here is an example of how to initialize the ESSI.

Put the ESSI in its individual reset state by clearing the PCR bits.

Configure the control registers (CRA, CRB) to set the operating mode. Disable the

transmitters and receiver by clearing the TE[2–0] and RE bits. Set the interrupt enable

bits for the operating mode chosen.

Enable the ESSI by setting the PCR bits to activate the input/output signals to be used.

Write initial data to the transmitters that are in use during operation. This step is needed

even if DMA services the transmitters.

Enable the transmitters and receiver to be used.

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