DSP56303 datasheet(163/292 Pages) FREESCALE

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ESSI Programming Model

DSP56303 User’s Manual, Rev. 2

Freescale Semiconductor

7-31

7.5.7 ESSI Transmit Data Registers (TX[2–0])

ESSI0:TX20, TX10, TX00; ESSI1:TX21, TX11, TX01

TX2, TX1, and TX0 are 24-bit write-only registers. Data written into these registers

automatically transfers to the transmit shift registers. (See Figure 7-12 and Figure 7-13.) The

data transmitted (8, 12, 16, or 24 bits) is aligned according to the value of the ALC bit. When the

ALC bit is cleared, the MSB is Bit 23. When ALC is set, the MSB is Bit 15. If the transmit data

Note:

When data is written to a peripheral device, there is a two-cycle pipeline delay while

any status bits affected by this operation are updated. If any of those status bits are read

during the two-cycle delay, the status bit may not reflect the current status.

7.5.8 ESSI Time Slot Register (TSR)

TSR is effectively a write-only null data register that prevents data transmission in the current

transmit time slot. For timing purposes, TSR is a write-only register that behaves as an alternative

transmit data register, except that, rather than transmitting data, the transmit data signals of all the

enabled transmitters are in the high-impedance state for the current time slot.

7.5.9 Transmit Slot Mask Registers (TSMA, TSMB)

Both transmit slot mask registers are read/write registers. When the TSMA or TSMB is read to

the internal data bus, the register contents occupy the two low-order bytes of the data bus, and the

high-order byte is filled by 0. In Network mode the transmitter(s) use these registers to determine

which action to take in the current transmission slot. Depending on the bit settings, the

transmitter(s) either tri-state the transmitter(s) data signal(s) or transmit a data word and generate

a transmitter empty condition.

TS15

TS14

TS13

TS12

TS11

TS10

TS9

TS8

TS7

TS6

TS5

TS4

TS3

TS2

TS1

TS0

—Reserved bit; read as 0; write to 0 0 for future compatibility.

(ESSI0 X:$FFFFB4, ESSI1 X:$FFFFA4)

Figure 7-14. ESSI Transmit Slot Mask Register A (TSMA)

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