UPSD3422EB40U6 datasheet(70/293 Pages) STMICROELECTRONICS

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17.1.1

GPIO function

Ports in GPIO mode operate as quasi-bidirectional pins, consistent with standard 8051

architecture. GPIO pins are individually controlled by three SFRs:

●

SFR, P1 (Table 27 on page 73)

●

SFR, P3 (Table 28 on page 73)

●

SFR, P4 (Table 29 on page 74)

These SFRs can be accessed using the Bit Addressing mode, an efficient way to control

individual port pins.

17.1.2

GPIO output

Simply stated, when a logic '0' is written to a bit in any of these port SFRs while in GPIO

mode, the corresponding port pin will enable a low-side driver, which pulls the pin to ground,

and at the same time releases the high-side driver and pull-ups, resulting in a logic '0'

output. When a logic '1' is written to the SFR, the low-side driver is released, the high-side

driver is enabled for just one MCU_CLK period to rapidly make the 0-to1 transition on the

pin, while weak active pull-ups (total ~150K

Ω) to V

CC are enabled. This structure is

consistent with standard 8051 architecture. The high side driver is momentarily enabled only

for 0-to-1 transitions, which is implemented with the delay function at the latch output as

pictured in Figure 17 on page 71, Figure 18 on page 72, and Figure 19 on page 72. After

the high-side driver is disabled, the two weak pull-ups remain enabled resulting in a logic '1'

output at the pin, sourcing IOH uA to an external device. Optionally, an external pull-up

resistor can be added if additional source current is needed while outputting a logic '1.'

17.1.3

GPIO input

To use a GPIO port pin as an input, the low-side driver to ground must be disabled, or else

the true logic level being driven on the pin by an external device will be masked (always

reads logic '0'). So to make a port pin “input ready”, the corresponding bit in the SFR must

have been set to a logic '1' prior to reading that SFR bit as an input. A reset condition forces

SFRs P1, P3, and P4 to FFh, thus all three ports are input ready after reset.

When a pin is used as an input, the stronger pull-up “A” maintains a solid logic '1' until an

external device drives the input pin low. At this time, pull-up “A” is automatically disabled,

and only pull-up “B” will source the external device IIH uA, consistent with standard 8051

architecture.

GPIO Bi-Directional. It is possible to operate individual port pins in bi-directional mode. For

an output, firmware would simply write the corresponding SFR bit to logic '1' or '0' as

needed. But before using the pin as an input, firmware must first ensure that a logic '1' was

the last value written to the corresponding SFR bit prior to reading that SFR bit as an input.

GPIO Current Capability. A GPIO pin on Port 4 can sink twice as much current than a pin

on either Port 1 or Port 3 when the low-side driver is outputting a logic '0' (IOL). See the DC

specifications at the end of this document for full details.

Reading Port Pin vs. Reading Port Latch. When firmware reads the GPIO ports,

sometimes the actual port pin is sampled in hardware, and sometimes the port SFR latch is

read and not the actual pin, depending on the type of MCU instruction used. These two data

paths are shown in Figure 17 on page 71 through Figure 19 on page 72. SFR latches are

read (and not the pins) only when the read is part of a read-modify-write instruction and the

write destination is a bit or bits in a port SFR. These instructions are: ANL, ORL, XRL, JBC,

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