UPSD3422EB40U6 datasheet(46/293 Pages) STMICROELECTRONICS

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uPSD34xx instruction set summary

uPSD34xx

46/293

Note:

All mnemonics copyrighted ©Intel Corporation 1980.

Table 11.

Miscellaneous instruction set

Note:

All mnemonics copyrighted ©Intel Corporation 1980.

Table 12.

Notes on instruction set and addressing modes

CJNE

@Ri, #data,

rel

Compare immediate to indirect, jump if not equal

3 byte/2 cycle

DJNZ

Rn, rel

Decrement register and jump if not zero

2 byte/2 cycle

DJNZ

direct, rel

Decrement direct byte and jump if not zero

3 byte/2 cycle

Mnemonic(1) and Use

Description

Length/Cycles

Mnemonic(1) and Use

Description

Length/Cycles

Miscellaneous

NOP

No Operation

1 byte/1 cycle

direct

8-bit address for internal 8032 DATA SRAM (locations 00h - 7Fh) or SFR registers

(locations 80h - FFh).

@Ri

8-bit internal 8032 SRAM (locations 00h - FFh) addressed indirectly through contents of

R0 or R1.

#data

8-bit constant included within the instruction.

#data16 16-bit constant included within the instruction.

addr16

16-bit destination address used by LCALL and LJMP.

addr11

11-bit destination address used by ACALL and AJMP.

rel

Signed (two-s compliment) 8-bit offset byte.

bit

Direct addressed bit in internal 8032 DATA SRAM (locations 20h to 2Fh) or in SFR

registers (88h, 90h, 98h, A8h, B0, B8h, C0h, C8h, D0h, D8h, E0h, F0h).

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