Motore di ricerca datesheet componenti elettronici
  Italian  ▼
ALLDATASHEETIT.COM

X  

Preview PDF HTML

PCM1774 Scheda tecnica(PDF) 22 Page - Texas Instruments

Click here to check the latest version.
Il numero della parte PCM1774
Spiegazioni elettronici  16-Bit, Low-Power Stereo Audio DAC With Analog Mixing, Line and Headphone Outputs
PDF  49 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Produttore elettronici  TI [Texas Instruments]
Homepage  http://www.ti.com
Logo TI - Texas Instruments

PCM1774 Scheda tecnica(HTML) 22 Page - Texas Instruments

Back Button PCM1774 Datasheet HTML 18Page - Texas Instruments PCM1774 Datasheet HTML 19Page - Texas Instruments PCM1774 Datasheet HTML 20Page - Texas Instruments PCM1774 Datasheet HTML 21Page - Texas Instruments PCM1774 Datasheet HTML 22Page - Texas Instruments PCM1774 Datasheet HTML 23Page - Texas Instruments PCM1774 Datasheet HTML 24Page - Texas Instruments PCM1774 Datasheet HTML 25Page - Texas Instruments PCM1774 Datasheet HTML 26Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 22 / 49 page
background image
www.ti.com
R0002-02
M: Master Device S: Slave Device St: Start Condition
Sr: Repeated Start Condition ACK: Acknowledge Sp: Stop Condition NACK: Not Acknowledge
W: Write R: Read
Transmitter
M
M
M
S
Data Type
St
Slave Address
W
ACK
M
Reg Address
M
Sr
M
Slave Address
S
ACK
M
R
S
ACK
M
Sp
M
NACK
S
Read Data
Timing Diagram
PCM1774
SLAS551 – JULY 2007
NOTE: The slave address after the repeated start condition must be the same as the previous slave address.
Figure 22. Read Operation
PARAMETERS
CONDITIONS
MIN
MAX
UNIT
fSCL
SCL clock frequency
Standard
100
kHz
t(BUF)
Bus free time between a STOP and START condition
Standard
4.7
μs
t(LOW)
Low period of the SCL clock
Standard
4.7
μs
t(HI)
High period of the SCL clock
Standard
4
μs
t(RS-SU)
Setup time for START condition
Standard
4.7
μs
t(S-HD)
Hold time for START condition
Standard
4
μs
t(D-SU)
Data setup time
Standard
250
ns
t(D-HD)
Data hold time
Standard
0
900
ns
t(SCL-R)
Rise time of SCL signal
Standard
20 + 0.1 CB
1000
ns
t(SCL-R1)
Rise time of SCL signal after a repeated START condition and
Standard
20 + 0.1 CB
1000
ns
after an acknowledge bit
t(SCL-F)
Fall time of SCL signal
Standard
20 + 0.1 CB
1000
ns
t(SDA-R)
Rise time of SDA signal
Standard
20 + 0.1 CB
1000
ns
t(SDA-F)
Fall time of SDA signal
Standard
20 + 0.1 CB
1000
ns
t(P-SU)
Setup time for STOP condition
Standard
4
μs
CB
Capacitive load for SDA and SCL line
400
pF
t(SP)
Pulse duration of suppressed spike
25
ns
Figure 23. I2C Interface Timing
22
Submit Documentation Feedback



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49


Scheda tecnica Scarica

Go To PDF Page


Link URL



Lei ha avuto il aiuto da alldatasheet?  [ DONATE ] 

Di alldatasheet   |   Richest di pubblicita   |   contatti   |   Privacy Policy   |   Collegamento alla scheda tecnica    |   scambio Link   |   Ricerca produttore
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com