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MPC8358E Scheda tecnica(PDF) 73 Page - Freescale Semiconductor, Inc

Il numero della parte MPC8358E
Spiegazioni elettronici  PowerQUICC??II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications
PDF  96 Pages
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Produttore elettronici  FREESCALE [Freescale Semiconductor, Inc]
Homepage  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8358E Scheda tecnica(HTML) 73 Page - Freescale Semiconductor, Inc

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MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1
Freescale Semiconductor
73
Package and Pin Listings
GVDD
C19, C22, C25, G24, J18, J19, J20, J24, K19, K20, K26,
L20, M20, M26, N19, N20, P20, P27, R20, T19, T20, T27,
U19, U20, U25, V19, V20, W20, W26, Y20, AA24, AB28,
AC21, AC28, AD28, AF21, AF25
Power for
DDR
DRAM
I/O
Voltage
(2.5 V or
1.8 V)
GVDD
LVDD0F3, J9
LVDD0
LVDD1P3, P10
LVDD110
LVDD2R4, R10
LVDD210
VDD
M12, M13, M16, M17, N10, N12, N13, N14, N15, N16,
N17, P12, P13, P14, P15, P16, P17, R12, R13, R16,
R17, T12, T13, T16, T17, U12, U13, U14, U15, U16, U17,
V12, V13, V16, V17, W11, W12, W13, W15, W16, W17,
Y16, Y17
Power for
Core
(1.2 V)
VDD
OVDD
C6, C12, D17, J11, J13, J14, K3, K9, K10, K12, K15,
K16, L10, M9, N9, T9, U9, V3, V10, W9, W10, W14, Y9,
Y10, Y12, Y13, Y15, AA3, AE6, AE16, AF11, AF20
PCI,
10/100
Ethernet,
and other
Standard
(3.3 V)
OVDD
MVREF1
J27
I
DDR
Referen
ce
Voltage
MVREF2
Y24
I
DDR
Referen
ce
Voltage
No Connect
NC
F23, G23, H23, J23, K23, L23, M23, N23, P23, R23, T23,
U23, V23, W23, Y23, AA23, AB23, AC23
——
—
Notes:
1. This pin is an open drain signal. A weak pull-up resistor (1 k
Ω) should be placed on this pin to OVDD.
2. This pin is an open drain signal. A weak pull-up resistor (2–10 k
Ω) should be placed on this pin to OVDD.
3. This output is actively driven during reset rather than being three-stated during reset.
4. These JTAG pins have weak internal pull-up P-FETs that are always enabled.
5.This pin should have a weak pull up if the chip is in PCI host mode. Follow PCI specifications recommendation.
6. These are On Die Termination pins, used to control DDR2 memories internal termination resistance.
7. This pin must always be tied to GND.
8. This pin must always be left not connected.
9. This pin must always be tied to GVDD.
10. Refers to
MPC8360E PowerQUICC II™ Pro Integrated Communications Processor Reference Manual section on "RGMII
Pins" for information about the two UCC2 Ethernet interface options.
11. It is recommended that MDIC0 be tied to GND using an 18.2
Ω resistor and MDIC1 be tied to DDR power using an 18.2 Ω
resistor for DDR2.
Table 65. MPC8358E PBGA Pinout Listing (continued)
Signal
Package Pin Number
Pin Type
Power
Supply
Notes



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