MPC8358E datasheet(1/96 Pages) FREESCALE

Il numero della parte	MPC8358E

Spiegazioni elettronici	PowerQUICC??II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications

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Produttore elettronici	FREESCALE [Freescale Semiconductor, Inc]

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Freescale Semiconductor

Technical Data

This document provides an overview of the MPC8358E

PowerQUICC™ II Pro processor revision 2.1 PBGA

features, including a block diagram showing the major

functional components. This device is a cost-effective,

highly integrated communications processor that addresses

the needs of the networking, wireless infrastructure and

telecommunications markets. Target applications include

next generation DSLAMs, network interface cards for 3G

basestations (Node Bs), routers, media gateways and high

end IADs. The device extends current PowerQUICC II Pro

offerings, adding higher CPU performance, additional

functionality, faster interfaces and robust interworking

between protocols while addressing the requirements related

to time-to-market, price, power, and package size. This

device can be used for the control plane along with data

plane functionality.

For functional characteristics of the processor, refer to the

MPC8360E PowerQUICC™ Pro Integrated

Communications Processor Family Reference Manual,

Rev. 2.

To locate any published errata or updates for this document,

contact your Freescale sales office.

Document Number: MPC8358EEC

Rev. 1, 12/2007

Contents

1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

2. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . 7

3. Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 12

4. Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5. RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 14

6. DDR and DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . 17

7. DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

8. UCC Ethernet Controller: Three-Speed Ethernet, MII

Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

9. Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

10. JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

11. I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

12. PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

13. Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

14. GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

15. IPIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

16. SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

17. TDM/SI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

18. UTOPIA/POS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

19. HDLC, BISYNC, Transparent, and Synchronous

UART. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

20. USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

21. Package and Pin Listings . . . . . . . . . . . . . . . . . . . . . . 66

22. Clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

23. Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

24. System Design Information . . . . . . . . . . . . . . . . . . . . 90

25. Document Revision History. . . . . . . . . . . . . . . . . . . . 94

26. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . 94

MPC8358E

PowerQUICC™ II Pro Processor

Revision 2.1 PBGA Silicon

Hardware Specifications

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