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P-Channel Logic Level Enhancement
Mode Field Effect Transistor
P2003EVG
SOP-8
Lead-Free
NIKO-SEM
2
OCT-20-2004
DYNAMIC
Input Capacitance
Ciss
1610
Output Capacitance
Coss
410
Reverse Transfer Capacitance
Crss
VGS = 0V, VDS = -15V, f = 1MHz
200
pF
Total Gate Charge
2
Qg
17
24
Gate-Source Charge
2
Qgs
5
Gate-Drain Charge
2
Qgd
VDS = 0.5V(BR)DSS, VGS = -10V,
ID = -9A
6
nC
Turn-On Delay Time
2
td(on)
5.7
Rise Time
2
tr
VDS = -15V, RL = 1Ω
10
Turn-Off Delay Time
2
td(off)
ID ≅ -1A, VGS = -10V, RGS = 6Ω
18
Fall Time
2
tf
5
nS
SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS (TC = 25 °C)
Continuous Current
IS
-2.1
Pulsed Current
3
ISM
-4
A
Forward Voltage
1
VSD
IF = -1A, VGS = 0V
-1.2
V
1Pulse test : Pulse Width
≤ 300 µsec, Duty Cycle ≤ 2％.
2Independent of operating temperature.
3Pulse width limited by maximum junction temperature.
REMARK: THE PRODUCT MARKED WITH “P2003EVG”, DATE CODE or LOT #
Orders for parts with Lead-Free plating can be placed using the PXXXXXXG parts name.
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