TUSB4041IPAP datasheet(28/48 Pages) TI2

28 / 48 page

TUSB4041I

SLLSEK3E – JULY 2015 – REVISED SEPTEMBER 2017

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8.5.22 Additional Feature Configuration Register

Offset = F0h

Figure 23. Additional Feature Configuration Register

RSVD

stsOutputEn

pwronTime

RSVD

R-0

R/RW-0

R/W-0

Table 24. Additional Feature Configuration Register Field Descriptions

Bit

Field

Type

Reset

Description

7:5

RSVD

Reserved

Read only, returns 0 when read.

RSVD

R/RW

Reserved.

3:1

pwronTime

Power-on delay time

When OTP ROM pwronTime field is all 0, this field sets the delay time from the

removal disable of PWRCTL to the enable of PWRCTL when transitioning battery

charging modes. For example, when disabling the power on a transition from a

custom charging mode to dedicated charging port mode. The nominal timing is

defined as follows:

TPWRON_EN = (pwronTime + 1) x 200 ms

(1)

This field may be overwritten by EEPROM contents or by an SMBus host.

RSVD

Reserved

8.5.23 Device Status and Command Register

Offset = F8h

Figure 24. Device Status and Command Register

RSVD

smbusRst

cfgActive

R-0

W1S-0

W1C-0

Table 25. Device Status and Command Register Field Descriptions

Bit

Field

Type

Reset

Description

7:2

RSVD

Reserved

Read only, returns 0 when read

smbusRst

W1S

SMBus interface reset

This bit loads the registers back to their GRSTz values.

This bit is set by writing a 1 and is cleared by hardware on completion of the reset. A

write of 0 has no effect.

cfgActive

W1C

Configuration active

This bit indicates that configuration of the TUSB4041I device is currently active. The

bit is set by hardware when the device enters the I2C or SMBus mode. The

TUSB4041I device does not connect on the upstream port while this bit is 1.

When in the SMBus mode, this bit must be cleared by the SMBus host to exit the

configuration mode and allow the upstream port to connect.

The bit is cleared by a writing 1. A write of 0 has no effect.

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