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TSC2014 Scheda tecnica(PDF) 7 Page - Texas Instruments |
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TSC2014 Scheda tecnica(HTML) 7 Page - Texas Instruments |
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7 / 62 page  7 TSC2014 www.ti.com SBAS484B – SEPTEMBER 2010 – REVISED DECEMBER 2016 Product Folder Links: TSC2014 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated (1) Refer to Figure 36. 6.6 Timing Requirements for Figure 1: I 2C Standard Mode (f SCL = 100 kHz) All specifications typical at –40°C to +85°C, VDD = +1.2V to +3.6V, unless otherwise noted. TWO-WIRE STANDARD MODE PARAMETERS TEST CONDITIONS MIN MAX UNIT Reset low time(1) tWL(RESET) VDD ≥ 1.6V 10 μs 1.2V ≤ VDD < 1.6V 13 μs SCL clock frequency fSCL 100 kHz Bus free time between a STOP and START condition tBUF 4.7 μs Hold time (repeated) START condition tHD, STA 4.0 μs Low period of SCL clock tLOW 4.7 μs High period of the SCL clock tHIGH 4.0 μs Setup time for a repeated START condition tSU, STA 4.7 μs Data hold time tHD, DAT 0 3.45 μs Data setup time tSU, DAT 250 ns Rise time of both SDA and SCL signals tR Cb = total bus capacitance 1000 ns Fall time of both SDA and SCL signals tF Cb = total bus capacitance 300 ns Setup time for STOP condition tSU, STO 4.0 μs Capacitive load for each bus line Cb Cb = total capacitance of one bus line in pF 400 pF Pulse width of spike suppressed tSP N/A N/A ns (1) Refer to Figure 36. (2) Cb = the total capacitance of one bus line in pF. If using both Fast mode and Hs-mode devices, faster fall times according to the 3.4MHz High-Speed Mode table are allowed. Note that the TSC2014 is a Hs-mode device and follows the I2C, 3.4MHz, High-Speed Mode table requirements. 6.7 Timing Requirements for Figure 1: I 2C Fast Mode (f SCL = 400 kHz) All specifications typical at –40°C to +85°C, VDD = +1.2V to +3.6V, unless otherwise noted. TWO-WIRE FAST MODE PARAMETERS TEST CONDITIONS MIN MAX UNIT Reset low time(1) tWL(RESET) VDD ≥ 1.6V 10 μs 1.2V ≤ VDD < 1.6V 13 μs SCL clock frequency fSCL 400 kHz Bus free time between a STOP and START condition tBUF 1.3 μs Hold time (repeated) START condition tHD, STA 0.6 μs Low period of SCL clock tLOW 1.3 μs High period of the SCL clock tHIGH 0.6 μs Setup time for a repeated START condition tSU, STA 0.6 μs Data hold time tHD, DAT 0 0.9 μs Data setup time tSU, DAT 100 ns Rise time of both SDA and SCL signals tR Cb = total bus capacitance 20 + 0.1 × Cb 300 ns Fall time of both SDA and SCL signals(2) tF Cb = total bus capacitance 20 + 0.1 × Cb 300 ns Setup time for STOP condition tSU, STO 0.6 μs Capacitive load for each bus line Cb Cb = total capacitance of one bus line in pF 400 pF Pulse width of spike suppressed tSP 0 50 ns |
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