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20MHz MODE

POWER-DOWN (PD)

5MHz MODE

60MHz MODE

POWER SUPPLIES

ANALOG POWER DISSIPATION

RBIAS

RBIAS

AGND

ADS1610

ADS1610

SBAS344C – AUGUST 2005 – REVISED OCTOBER 2006

Table 4. Four Modes of Operation(1)

Mode 1

Mode 0

OUTPUT RATE

OSR

SNR (TYP)

BITS

SETTLING TIME (DRDY cycles)

0

0

Default 10MHz mode

6

86dBFS

16

55

0

1

20MHz

3

74dBFS

14

25

1

0

5MHz

12

91dBFS

16

55

1

1

60MHz bypass mode

1

55dBFS

12

NA

(1)

There is a pull-down resistor of 170k

Ω on both mode pins; however, it is recommended that this pin be reduced to either high or low.

Table 5. Recommended RBIAS Resistor Values

In this mode, the oversampling ratio is three.

for Different CLK Frequencies

Decreasing the OSR from 6 to 3 doubles the data

fCLK

DATA

RBIAS

TYPICAL POWER

rate, at the same time the performance is reduced

RATE

DISSIPATION

from 16 bits to 14 bits. Note that all 16 bits of DOUT

42MHz

7MHz

45k

Ω

550mW

remain active in this mode. For fclk = 60MHz, the

48MHz

8MHz

37k

Ω

640mW

data rate is 20MSPS. In addition, the group delay

54MHz

9MHz

31k

Ω

720mW

becomes 1

µs or 13 DRDY cycles. In this mode the

noise increases. Typical SNR performance degrades

60MHz

10MHz

19k

Ω

960mW

by 14dB. THD remains approximately the same.

When not in use, the ADS1610 can be powered

In this mode the OSR is 12 for fclk = 60MHz and the

down by taking the PD pin low. There is an internal

data rate in 5MSPS. Typical SNR performance

pull-up resistor of 170k

Ω on the PD pin, but it is

increases by 4dB. THD remains approximately the

recommended that this pin be connected to DVDD if

same.

not used. Once the PD pin is pulled high, allow at

least t11 (see Timing Specification Table) DRDY

cycles for the modulator and the digital filter to settle

before retrieving data.

In this mode, decimation filters are bypassed. This

data output can be filtered externally by the user. For

fclk = 60MHz, the data rate is 60MSPS.

Two supplies are used on the ADS1610: analog

(AVDD), and digital (DVDD). Each supply (other than

DVDD pins 49 and 50) must be suitably bypassed to

An external resistor connected between the RBIAS

achieve the best performance. It is recommended

pin and the analog ground sets the analog current

that a 1

µF and 0.1µF ceramic capacitor be placed as

level, as shown in Figure 40. The current is inversely

close to each supply pin as possible. Connect each

proportional to the resistor value. Table 5 shows the

supply-pin

bypass

capacitor

to

the

associated

recommended values of RBIAS for different CLK

ground, as shown in Figure 41. Each main supply

frequencies. Notice that the analog current can be

bus should also be bypassed with a bank of

reduced when using a slower frequency CLK input

capacitors from 47

µF to 0.1µF, as shown in

because the modulator has more time to settle.

Figure 41.

Avoid adding any capacitance in parallel to RBIAS,

since this will interfere with the internal circuitry used

For optimum performance, insert a 10

Ω resistor in

to set the biasing.

series with the AVDD2 supply (pin 58); the modulator

clocking circuitry. This resistor decouples switching.

Figure 40. External Resistor Used to Set

Analog Power Dissipation

19

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