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ADS1610IPAPR Scheda tecnica(PDF) 6 Page - Texas Instruments |
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ADS1610IPAPR Scheda tecnica(HTML) 6 Page - Texas Instruments |
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6 / 29 page ![]() www.ti.com TIMING SPECIFICATIONS CLK DRDY DOUT[15:0] Data N Data N + 1 Data N + 2 t 1 t 2 t 4 t 4 t 6 t 2 t 3 t 5 RD, CS DOUT[15:0] t 7 t 8 ADS1610 SBAS344C – AUGUST 2005 – REVISED OCTOBER 2006 TERMINAL FUNCTIONS (continued) TERMINAL ANALOG/DIGITAL DESCRIPTION INPUT/OUTPUT NAME NO. RD 22 Digital input; Active low Read enable OTR 23 Digital output Analog inputs out-of-range DRDY 24 Digital output Data ready DOUT[15:0] 29–44 Digital output Data output. DOUT[15] is the MSB and DOUT[0] is the LSB. CLK 56 Digital input Clock input AGND2 57 Analog Analog ground for AVDD2 AVDD2 58 Analog Analog supply for modulator clocking VCAP 59 Analog Bypass capacitor VREFN 60, 61 Analog Negative reference voltage VMID 62 Analog Midpoint voltage VREFP 63, 64 Analog Positive reference voltage Figure 1. Data Retrieval Timing Figure 2. DOUT Inactive/Active Timing 6 Submit Documentation Feedback |
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