ADS1610IPAPR.B datasheet(16/29 Pages) TI2

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101

100

10−1

10−2

10−3

10−4

10−5

Settling Time (DRDY cycles)

IMPULSE RESPONSE

ADS1610

CLK

SYNC

Clock

ADS1610

CLK

SYNC

Synchronized

Settled

Data

Settled

Data

DRDY1

DRDY

DOUT[15:0]1

DOUT[15:0]

DOUT[15:0]2

DRDY2

SYNC

DRDY1

DOUT[15:0]1

CLK

SYNC

DRDY

DOUT[15:0]

SETTLING TIME

1.0

0.8

0.6

0.4

0.2

−0.2

−0.4

Time (DRDY cycles)

ADS1610

SBAS344C – AUGUST 2005 – REVISED OCTOBER 2006

Figure 32 shows the settling error as a function of

time for a full-scale signal step applied at t = 0, with

MODE = 00 (See Table 4). This figure uses DRDY

cycles for the ADS1610 for the time scale (X-axis).

After 55 DRDY cycles, the settling error drops below

0.001%. For fCLK = 60MHz, this corresponds to a

settling time of 5.5

µs.

Figure 32. Settling Time

Figure 33 plots the normalized response for an input

applied at t = 0, with MODE = 00. The X-axis units of

time are DRDY cycles for the ADS1610. As shown in

Figure 33, the peak of the impulse takes 30 DRDY

cycles to propagate to the output. For fCLK = 60 MHz,

a DRDY

cycle

0.1

µs in duration and the

propagation time (or group delay) is 30 × 0.1

µs =

Figure 31. Synchronizing Multiple Converters

3.0

µs.

The settling time is an important consideration when

measuring signals with large steps or when using a

multiplexer in front of the analog inputs. The

ADS1610

digital

filter

requires

time

for

instantaneous change in signal level to propagate to

the output.

Be sure to allow the filter time to settle after applying

a large step in the input signal, switching the channel

on a multiplexer placed in front of the inputs,

resetting the ADS1610, or exiting the power-down

mode.

Figure 33. Impulse Response

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