ADS1610IPAPR.B datasheet(12/29 Pages) TI2

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OVERVIEW

ANALOG INPUTS (AINP, AINN)

signal,

CM +

AINP ) AINN

is 2.5V.

*0.1 V t (AINN or AINP) t 4.2 V

(1)

Σ∆

Modulator

Digital

Filter

Parallel

Interface

REF

VREFN

VREFP

AINP

AINN

MODE[1:0]

OTR

DOUT[15:0]

INPUT CIRCUITRY

ADS1610

SBAS344C – AUGUST 2005 – REVISED OCTOBER 2006

The ADS1610 is a high-performance, delta-sigma

The ADS1610 supports a very wide range of input

ADC. The modulator uses an inherently stable,

signals. Having such a wide input range makes

pipelined,

delta-sigma

modulator

architecture

out-of-range signals unlikely. However, should an

incorporating proprietary circuitry that allows for very

out-of-range signal occur, the digital output OTR will

linear high-speed operation. The modulator samples

go high.

the input signal at 60MSPS (when fCLK = 60MHz). A

To achieve the highest analog performance, it is

low-ripple linear phase digital filter decimates the

recommended that the inputs be limited to no greater

modulator output by 6 to provide data output word

than 0.891VREF (-1dBFS). For VREF = 3V, the

rates of 10MSPS with a signal passband out to

corresponding recommended input range is 2.67V.

4.9MHz.

The analog inputs must be driven with a differential

Conceptually,

the

modulator

and

digital

filter

signal

achieve

optimum

performance.

The

measure the differential input signal, VID = (AINP –

recommended common-mode voltage of the input

AINN), against the differential reference, Vref =

(VREFP – VREFN), as shown in Figure 11. A 16-bit

parallel data bus, designed for direct connection to

DSPs, outputs the data. A separate power supply for

In addition to the differential and common-mode

the I/O allows flexibility for interfacing to different

input voltages, the absolute input voltage is also

logic families. Out-of-range conditions are indicated

important. This is the voltage on either input (AINP or

with a dedicated digital output pin. Analog power

AINN) with respect to AGND. The range for this

dissipation is controlled using an external resistor.

voltage is:

This allows reduced dissipation when operating at

slower speeds. When not in use, power consumption

can be dramatically reduced using the PD pin.

If either input is taken below –0.1V, ESD protection

diodes on the inputs will turn on. Exceeding 4.2V on

either input will result in linearity performance

degradation. ESD protection diodes will also turn on

if the inputs are taken above AVDD (+5V).

Figure 24. Conceptual Block Diagram

circuits. Switches S2 represent the net effect of the

modulator circuitry in discharging the sampling

capacitors, the actual implementation is different.

The ADS1610 uses switched-capacitor circuitry to

The timing for switches S1 and S2 is shown in

measure the input voltage. Internal capacitors are

Figure 26.

charged by the inputs and then discharged internally

with this cycle repeating at the frequency of CLK.

Figure 25 shows a conceptual diagram of these

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