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AFE5804 Scheda tecnica(PDF) 17 Page - Texas Instruments |
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AFE5804 Scheda tecnica(HTML) 17 Page - Texas Instruments |
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17 / 82 page ![]() GND Logic 0 OUTP OUTM GND Logic 0 V = -350 mV* ODL Logic 0 V = +350 mV* ODH VOCM *With external 100- termination W POWER SUPPLY AVDD, LVDD RESET SEN t 1 t 2 t 3 17 ADS5294 www.ti.com SLAS776E – NOVEMBER 2011 – REVISED APRIL 2018 Product Folder Links: ADS5294 Submit Documentation Feedback Copyright © 2011–2018, Texas Instruments Incorporated (1) A high-going pulse on RESET pin is required in serial interface mode in case of initialization through hardware reset. Tie RESET permanently HIGH for parallel interface operation. (2) SEN refers to the CSZ pin. Figure 1. Reset Timing Diagram Figure 2. LVDS Output Voltage Levels |
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