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AM263P4 Scheda tecnica(PDF) 146 Page - Texas Instruments |
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AM263P4 Scheda tecnica(HTML) 146 Page - Texas Instruments |
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146 / 168 page  6.11.6 Emulation and Debug For more details about features and additional description information on the device Trace and JTAG interfaces, see the corresponding subsections within Signal Descriptions and Detailed Description sections. For more information, see the On-Chip Debug section in the device TRM. 6.11.6.1 JTAG The acronym stands for the Joint Test Action Group, the committee of engineers who defined the boundary- scan standard (IEEE std 1149.1). For more details about features and additional description information on the device JTAG interface, see the corresponding subsections within Signal Descriptions and Detailed Description sections. 6.11.6.1.1 JTAG Timing Conditions PARAMETER MIN MAX UNIT INPUT CONDITIONS SRI Input Slew Rate 0.5 2.00 V/ns OUTPUT CONDITIONS CL Output Load Capacitance 5 15 pF 6.11.6.1.2 JTAG Timing Requirements NO. PARAMETER DESCRIPTION MIN MAX UNIT J1 tc(TCK) Cycle time, TCK 40 ns J2 tw(TCKH) Pulse width, TCK high 16 ns J3 tw(TCKL) Pulse width, TCK low 16 ns J4 tsu(TDI-TCKH) Input setup time, TDI valid to TCK high 2 ns tsu(TMS-TCKH) Input setup time, TMS valid to TCK high 2 J5 th(TCK-TDI) Input hold time, TDI valid from TCK high 15.9 ns th(TCK-TMS) Input hold time, TMS valid from TCK high 15.9 6.11.6.1.3 JTAG Switching Characteristics NO. PARAMETER DESCRIPTION MIN MAX UNIT J6 td(TCKL-TDOI) Delay time, TCK low to TDO invalid –0.067005 ns J7 td(TCKL-TDOV) Delay time, TCK low to TDO valid 11.89594 ns TDO J2 J1 J4 TCK J5 TDI / TMS J3 J6 J7 J4 J5 Figure 6-65. JTAG Timing Requirements and Switching Characteristics AM263P4, AM263P2, AM263P4-Q1, AM263P2-Q1 SPRSP81D – OCTOBER 2023 – REVISED MAY 2025 www.ti.com 146 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated Product Folder Links: AM263P4 AM263P2 AM263P4-Q1 AM263P2-Q1 |
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