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AM263P4 Scheda tecnica(PDF) 68 Page - Texas Instruments |
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AM263P4 Scheda tecnica(HTML) 68 Page - Texas Instruments |
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68 / 168 page  5.3.20 SDFM Table 5-99. SDFM0 Signal Descriptions SIGNAL NAME [1] PIN TYPE [2] DESCRIPTION [3] ZCZ C PIN [4] ZCZ S PIN [4] ZCZ F PIN [4] SDFM0_CLK0 I SDFM Channel 0 Clock B16 B16 B16 SDFM0_CLK1 I SDFM Channel 1 Clock A16 A16 A16 SDFM0_CLK2 I SDFM Channel 2 Clock B15 B15 B15 SDFM0_CLK3 I SDFM Channel 3 Clock A15 A15 A15 SDFM0_D0 I SDFM Channel 0 Data D14 D14 D14 SDFM0_D1 I SDFM Channel 1 Data D13 D13 D13 SDFM0_D2 I SDFM Channel 2 Data C13 C13 C13 SDFM0_D3 I SDFM Channel 3 Data C14 C14 C14 Table 5-100. SDFM1 Signal Descriptions SIGNAL NAME [1] PIN TYPE [2] DESCRIPTION [3] ZCZ C PIN [4] ZCZ S PIN [4] ZCZ F PIN [4] SDFM1_CLK0 I SDFM Channel 0 Clock B14, B6 B14, B6 B14, B6 SDFM1_CLK1 I SDFM Channel 1 Clock B5, C12 B5, C12 B5, C12 SDFM1_CLK2 (1) ID SDFM Channel 2 Clock A3, B13 A3, B13 A3, B13 SDFM1_CLK3 (2) I SDFM Channel 3 Clock A13, C6 A13, C6 A13, C6 SDFM1_D0 I SDFM Channel 0 Data A14, A4 A14, A4 A14, A4 SDFM1_D1 I SDFM Channel 1 Data B4, D11 B4, D11 B4, D11 SDFM1_D2 I SDFM Channel 2 Data A2, B12 A2, B12 A2, B12 SDFM1_D3 I SDFM Channel 3 Data A12, A5 A12, A5 A12, A5 (1) SDFM1_CLK2 is implemented with the I2C OD FS (Open Drain Fail Safe) voltage buffer. (2) SDFM1_CLK3 is implemented with the I2C OD FS (Open Drain Fail Safe) voltage buffer. 5.3.21 System and Miscellaneous 5.3.21.1 Boot Mode Configuration Table 5-101. Boot Mode Signal Descriptions SIGNAL NAME [1] PIN TYPE [2] DESCRIPTION [3] ZCZ C PIN [4] ZCZ S PIN [4] ZCZ F PIN [4] SOP0 I Boot Mode configuration bit 0 (OSPI0_D0) N1 N1 N1 SOP1 I Boot Mode configuration bit 1 (OSPI0_D1) N4 N4 N4 SOP2 I Boot Mode configuration bit 2 (SPI0_CLK) A11 A11 A11 SOP3 I Boot Mode configuration bit 3 (SPI0_D0) C10 C10 C10 5.3.21.2 Clocking Table 5-102. XTAL Signal Descriptions SIGNAL NAME [1] PIN TYPE [2] DESCRIPTION [3] ZCZ C PIN [4] ZCZ S PIN [4] ZCZ F PIN [4] XTAL_XI (1) I External Crystal (XTAL) Input T1 T1 T1 XTAL_XO (1) O External Crystal (XTAL) Output R1 R1 R1 (1) The XTAL interface requires a 25 MHz clock source. Table 5-103. Output Clock Signal Descriptions SIGNAL NAME [1] PIN TYPE [2] DESCRIPTION [3] ZCZ C PIN [4] ZCZ S PIN [4] ZCZ F PIN [4] CLKOUT0 O Output Clock 0 M2 M2 M2 CLKOUT1 O Output Clock 1 B16 B16 B16 Table 5-104. External Reference Clock Signal Descriptions SIGNAL NAME [1] PIN TYPE [2] DESCRIPTION [3] ZCZ C PIN [4] ZCZ S PIN [4] ZCZ F PIN [4] EXT_REFCLK0 I External Reference Clock Input P2 P2 P2 AM263P4, AM263P2, AM263P4-Q1, AM263P2-Q1 SPRSP81D – OCTOBER 2023 – REVISED MAY 2025 www.ti.com 68 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated Product Folder Links: AM263P4 AM263P2 AM263P4-Q1 AM263P2-Q1 |
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