L9942 datasheet(27/40 Pages) STMICROELECTRONICS

27 / 40 page

L9942

SPI - control and status registers

Doc ID 11778 Rev 7

27/40

5.8

Auxiliary logic blocks

5.8.1

Fault condition

Logical level at pin D0 represents fault condition. It is valid from first high to low edge of

signal CLK up to transfer of data bit D12. Fault bit is an logical OR of:

Control and status register 6 bit 5 and 6 for open load, bit 7 reference current failure

(RERR) and

Control and status register 7 bit 0 to bit 7 for overcurrent, bit 8 and 9 failure at VS

(UV,OV) and

bit 10 and bit 11 during high temperature (TW,TSD)

5.8.2

SPI communication monitoring

At the rising edge of the CSN signal the contents of the shift register will be transferred to

the selected data register. A counter monitors proper SPI communication. It counts rising

edges at pin CLK. The writing to the register is only enabled if exactly 16 bits are transmitted

within one communication frame (i.e. CSN low). If more or less clock pulses are counted

within one frame the complete frame will be ignored. This safety function is implemented to

avoid an activation of the output stages by a wrong communication frame. SPI

communication can be checked by loading a command twice and then answer at pin DO

must be same.

Note:

Due to this safety functionality a daisy chaining of SPI is not possible. Instead, a parallel

operation of the SPI bus by controlling the CSN signal of the connected ICs is

recommended.

5.8.3

PWM monitoring for stall detection

Control registers 4, 5, and 3 contain bits D0-D7, use for setting a stall detection threshold.

The value in this set of bits determine the minimum time for current rise over one quadrant of

motor driving. D7-D0 is compared with the sum of the rise times over one quadrant. When

the sum is less than the value stored in D7-D0 the ST bit (register 6 bit 8) is set to a logic “1”.

The PWM pin reflects the PWM control signal of the load current in bridge A. This is so after

power on when the SST bit (register 6, bit11) is reset to a logic “0”. If this bit is set to a

logical “1” then status of the ST bit 8 is mirrored to pin PWM. This provides stall detection

without the need of reading register 6 through the SPI bus.

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