L9965T datasheet(36/62 Pages) STMICROELECTRONICS

36 / 62 page

5.8.2.1

Single read/write

When in NORMAL mode the device is available for SPI and VIF communication.

If the DEV_ID field in the SPI frame corresponds to the transceiver VIF_ID_CFG.VIF_ID register value, the frame

is checked (for CRC, length, register address) and, if correct, the internal register of L9965T, pointed by the

Address field, is accessed with out-of-frame approach.

If the DEV_ID field in the SPI frame does not correspond to the transceiver VIF_ID programmed value, the SPI

frame is checked (for CRC, length) and if correct, the frame is put in the TX_FIFO (depth 1).

The frame in TX FIFO is sent when the VIF interface is in IDLE state (readable in GEN_STATUS3.ISO_IDLE =1),

which means it is not already busy in a previous transmission task. When the transmission starts the TX FIFO is

cleared.

During transmission the VIF peripheral remains busy for a time that depends on the GEN_CFG5.

ISO_RX_TIMEOUT_ENB configuration bit value; the bit default value is zero and, in this case, the VIF returns

IDLE when transmission is completed; if the bit is set, the VIF remains busy to wait for an answer for an additional

time equal to WAIT_RX_BEGIN; when this timeout expires the VIF returns in IDLE state and is ready for a new

transmission.

In case of concurrent access from both SPI and VIF, the arbitration mechanism waits until VIF RX port is in IDLE

mode, then present the data to the VIF TX port to be transmitted.

If a new SPI frame is received to be transmitted on the VIF when TX FIFO is not empty, ongoing transmission

continues without interruption, but the previous frame in the TX FIFO is overwritten and the

GEN_STATUS1.FIFO_TX_FULL bit is set.

When a frame is received from the VIF the CRC and length are checked and, if correct, the frame is stored in the

first empty location of the VIF RX FIFO (depth 32) and the BNE pin is asserted. The VIF remains BUSY for a time

equal to WAIT_RX_END, then returns to IDLE state in case other frames must be received (i.e. Burst frame). This

timeout is disabled by default and can be enabled by bit GEN_CFG4. ISO_RX_TIMEOUT_ENB.

A FIFO_RX counter register (GEN_STATUS3.FIFO_RX_ADD) is incremented for each frame received and

decremented for each frame read. An SPI flush command is also available (writing 0xDC in CMD_REG) to clear

the entire RX FIFO.

When the microprocessor asserts the SPI NCS, L9965T/TS starts sending out on SDO the VIF RX FIFO content

with a FIFO approach. Each bit is sent synchronously with SCK provided by the microprocessor itself. The timings

of SDO with respect to SCK and NCS must follow the electrical characteristics listed in Table 30.

The first answer issued by the IC when, after a wakeup condition, it moves to NORMAL from DEEP SLEEP,

CYCLIC COUNT or CYCLIC_WAKEUP state is the default frame 0x0000000010 (see Section 5.8.3.4).

To enable interrupt-based communication with the BMS MCU, the BNE pin remains set until the VIF RX queue is

not empty (it contains at least an unread frame).

5.8.2.2

Burst read

To enable quick data retrieval from a specific chained L9965x AFEs, the IC implements a flexible burst read mode

available only on the VIF port. Burst packets can be requested performing a read access to L9965x specific

registers.

Two types of burst read can be requested:

•

Standard burst

–

L9965T/TS receives on the VIF a flexible number of registers, depending on L9965A setup (refer to

L9965A datasheet). This strategy can be used to quickly retrieve diagnostic and configuration data.

•

Compressed burst

–

L9965T/TS receives on the VIF a compressed packet according to L9965A setup (refer to L9965A

datasheet). This strategy is recommended to achieve high data rate with negligible impact on the

power consumption. It enables very fast conversion and readout threads, while keeping low power

consumption due to the reduced VIF transmitter duty-cycle.

Broadcast burst reads are not supported.

L9965T/TS features the decompressor for compressed burst frame, thus freeing MCU from implementing

complex routines to recover original cell/temperature/pack/busbar data.

As for all the received VIF frames, the packet CRC is checked and if correct, the information is formatted as in

Table 25 and stored in the VIF RX FIFO. The BNE pin is asserted.

When a compressed burst from L9965A is decompressed in the L9965T/TS RX FIFO, the FIFO contains variable

number of frames depending on the specific configuration of the addressed L9965A.

L9965T/L9965TS

Functional description

DS14987 - Rev 1

page 36/62

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