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L9965TS Scheda tecnica(PDF) 22 Page - STMicroelectronics |
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L9965TS Scheda tecnica(HTML) 22 Page - STMicroelectronics |
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22 / 62 page ![]() Fault type Assertion condition IC reaction to assertion Release condition Maskable • The FLT pin and the SPI FAULT is asserted in NORMAL if MSK_V5V_OC=0 in GEN_CFG3 for t>TV5V_UV_OV_FIL • FLT pin and SPI FAULT maskable by bit MSK_V5V_OC in GEN_CFG3 5.2.4.2 Electrical parameters Table 15. V5V electrical parameters Symbol Parameter Test conditions Min Typ Max Unit VV5V Regulated voltage NORMAL, All operating lines and loads -2% 5 +2% V IV5V_LIM Current limitation NORMAL, VV5V = 0V Tested in production -220 -80 mA CV5V External LDO capacitance Application info. Electrical parameters guaranteed from 1.6µF to 2.64µF. Stability down 0.8µF. 0.8 2 2.64 µF TV5V_SOFT_START Soft start timing From 10% to 90% of VV5V, Guaranteed by design 200 µs VV5V_UV_TH V5V Undervoltage Threshold Tested in production 4.25 4.75 V VV5V_UV_HYS V5V Undervoltage hysteresis Tested in production 50 150 mV VV5V_OV_TH V5V Overvoltage Threshold Tested in production 5.4 6 V VV5V_OV_HYS V5V Overvoltage hysteresis Tested in production 50 150 mV TV5V_UV_OV_FIL UV/OV filter time Tested by SCAN 17 23 µs ITH_OC_V5V V5V overcurrent monitor, threshold current -185 -145 -85 mA tFLT_OC_V5V V5V overcurrent monitor, detection filter time Digital filter 17 20 23 µs 5.3 Analog BIST The IC embeds an analog built-in self-test (BIST) to prevent latent failures affecting safety relevant comparators. In CYCLIC_WAKEUP state the BIST procedure is executed automatically within the diagnostic routine and it covers the following comparators: • V3V3 OV • V5V UV • V5V OV • GND LOSS The BIST procedure can be started in NORMAL state by setting GEN_CFG5.BIST_ANA_ENB = 1 in and covers the following comparators: • VB UV • V3V3 OV • V5V UV • V5V OV The bit GEN_STATUS3.BIST_ANA_DONE= 1 confirms the correct execution of the BIST procedure. L9965T/L9965TS Functional description DS14987 - Rev 1 page 22/62 |
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