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STA680 Scheda tecnica(PDF) 33 Page - STMicroelectronics |
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STA680 Scheda tecnica(HTML) 33 Page - STMicroelectronics |
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33 / 48 page  DS5877 Rev 13 33/48 STA680 Digital I/O and memory interfaces 47 5.5 Serial peripheral interfaces (SPI) The STA680 provides three serial peripheral interfaces: SPI1 is intended for communicating with the Host Microcontroller (slave); SPI2 interfaces the STA680 to the external flash memory (master); SPI3 - Reserved. Figure 11 shows the timing diagrams and waveform for the three SPI interfaces. Figure 11. SPI interface timings diagrams and waveforms Table 10 shows the timing values for the SPI interface used in application. Table 10. SPI interface timing values Symbol Parameter Working rate Unit Min. Max. Tss Chip select 8/Fsck - ns Fsck Serial bit clock, slave mode - 7056 kHz Fsck Serial bit clock, master mode - 28224 kHz Th Data hold time 7 - ns Ts Data setup time 15 - ns |
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