STA680 datasheet(41/48 Pages) STMICROELECTRONICS

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DS5877 Rev 13

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STA680

Electrical specifications

Output load for triple

voltage pads

3.3 V supply mode (for

both 4 mA and 8 mA)

60 MHz

75 MHz

CL,3V3

Output load for 3.3 V

pads

4 mA buffer

140 MHz

8 mA buffer

140 MHz

CL, DC

DC regulator output

load(12)

2.2

4.7

μF

1. DC operating voltage limits only apply for the case of external 1.8 V power supply. If connected to VDD_REG_1V8 supply

pad, DC operating voltage limits are covered by manufacturing tests.

2. Current consumption and power dissipation measured for single channel software application (HD 1.0) running at 127 MHz

on core and 65 MHz on SDRAM interface with FW version STA680-51001569-0D000003-C0004.000.

3. Current consumption and power dissipation measured for dual channel software application (HD 1.5) running at 127 MHz

on core and 130 MHz on SDRAM interface with FW version STA680-51001569-0D000033-C0004.000.

4. VDD_IO generally refers to the supply of the VDD_GEN_IO, VDD_FSH_IO and VDD_RAM_IO groups.

5. Performed on all the input pins excluded the pull-down and pull-up ones.

6. VDD_GEN_IO may be VDD_FHS_IO or VDD_GEN_IO depending on interface considered.

7. Performed only on the Input pins with pull up.

8. Performed only on the Input pins with pull down.

9. Guaranteed by Ipu measurements.

10. Guaranteed by Ipd measurements.

11. XmA = 4mA for a BD4, 8 mA for BD8 pad type.

12. Dielectric = X7R ESRmax = 100 ohm, 2.2 μF ±5% or any above 3 μF±10% but less than 4.7 μF±10%.It is also

recommended to distribute the 2.2 μF capacitance on the board by placing equivalent number of smaller capacitance value

(for example, 470 nF) near each VDD_REG1V8 supply pad.

Table 20. DC electrical characteristics (continued)

Symbol

Parameter

Test condition

Min.

Typ.

Max.

Unit

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