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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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STA1085 Scheda tecnica(PDF) 86 Page - STMicroelectronics |
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STA1085 Scheda tecnica(HTML) 86 Page - STMicroelectronics |
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86 / 127 page  Electrical Characteristics STA108x, STA109x 86/127 DS13319 Rev 2 4.17 SDRAM Interface Timing 4.17.1 SDRAM Interface Input Timings Table 51. SDRAM Input Timings Figure 25. SDRAM Input Timings 4.17.2 SDRAM Interface Output Timings Table 52. SDRAM Output Timings Symbol Parameter Timing Unit Cload [pF] Min Max Fc S Clock frequency - 166 MHz 10 tISU S Input setup time 0.3 - ns - tIH S Input hold time 1.5 - ns - tIH tpp = 1/Fc 50% VDD 50% VDD tISU SDRAM_FBCLK SDRAM DATA invalid Symbol Parameter Timing Unit Cload [pF] Min Max Fc S Clock frequency 166 MHz 10 tDO S Data output delay@166MHZ(1) 3.6 ns 10 tHO S Data hold time 1 ns 10 1. Internally data is launched at the negative edge of the clock. The output delay can be expressed as 1/Fc*0.55+.3. The multiplication factor 0f 0.55 is used to represent the duty cycle variation of the clock due to IO pads. 0.3 ns is the data travel time from the flop to the IO pad. At 112 MHz the max data output delay is 5.19 ns. |
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