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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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FC106 Scheda tecnica(PDF) 21 Page - STMicroelectronics |
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FC106 Scheda tecnica(HTML) 21 Page - STMicroelectronics |
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21 / 32 page  FC106 Revision 1.2 21/32 September 98 6.2 Receive interface timing 6.2.1 Receive clock timing and latency Figure 6.2 Receive clock timing Table 6.2 Receive clock timing characteristics Parameter Description Min Typ Max Units Trbc0 RBC[0] frequency1 1. Exact frequency of RBC(0,1) depends upon the received data frequency. During byte align- ment, the frequency of clocks RBC[0] and RBC[1] may vary by less than 1% of the specified typical value. The clocks are guaranteed to be glitch free. 53.125 MHz Trbc1 RBC[1] frequency1 53.125 MHz Trbc_skew RBC skew 8.9 - 9.9 ns RBC[0,1] Tr, Tf Receive clock rise and fall time (10pF load) - 2.5 - ns RBC[1] Trbc_skew RBC[0] Trbc0 1.4V 1.4V bit 0 of serial data TX+ Trbc1 |
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