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FC106 Scheda tecnica(PDF) 5 Page - STMicroelectronics |
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FC106 Scheda tecnica(HTML) 5 Page - STMicroelectronics |
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5 / 32 page ![]() FC106 Revision 1.2 5/32 September 98 The FC106 integrates a loop-back path for system-level test purposes. It also includes a self-test capability in which random patterns are transmitted through the internal loop-back path and compared after reception. The FC106 is implemented in a standard digital 0.35 µ CMOS process. Its typical power consumption is 0.4 Watts (not including the power required to drive the TTL parallel output port, which is in the 0.1 Watt range for output capacitive loads of 10 pF per pin). |
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