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M58PR512LE Scheda tecnica(PDF) 90 Page - Numonyx B.V |
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M58PR512LE Scheda tecnica(HTML) 90 Page - Numonyx B.V |
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90 / 123 page ![]() Part numbering M58PR512LE, M58PR001LE 90/123 17 Part numbering Devices are shipped from the factory with the memory content bits erased to ’1’. For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact the Numonyx sales office nearest to you. Table 36. Ordering information scheme Example: M58PR512L E 96 ZAD 5 Device type M58 Architecture P = multilevel, multiple bank, large buffer Operating voltage R = VDD = 1.7 V to 2.0 V, VDDQ = 1.7 V to 2.0 V Density 512 = 512 Mbit 001 = 1 Gbit Technology L = 65 nm technology multilevel design Memory organization E = uniform blocks Speed 96 = 96 ns Package ZAD = stacked TFBGA105 D stacked footprint. ZAC= stacked TFBGA107 C stacked footprint. Temperature range 5 = –30 to 85 °C |
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