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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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ST7LITEU09 Scheda tecnica(PDF) 96 Page - STMicroelectronics |
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ST7LITEU09 Scheda tecnica(HTML) 96 Page - STMicroelectronics |
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96 / 115 page  ST7LITEU05 ST7LITEU09 96/115 13.9 CONTROL PIN CHARACTERISTICS 13.9.1 Asynchronous RESET Pin TA = -40°C to 125°C, unless otherwise specified Notes: 1. Data based on characterization results, not tested in production. 2. The IIO current sunk must always respect the absolute maximum rating specified in section 13.2.2 on page 75 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. 3. The RON pull-up equivalent resistor is based on a resistive transistor. Specified for voltages on RESET pin between VILmax and VDD 4. To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses applied on RESET pin with a duration below th(RSTL)in can be ignored. Symbol Parameter Conditions Min Typ Max Unit VIL Input low level voltage VSS - 0.3 0.3xVDD V VIH Input high level voltage 0.7xVDD VDD + 0.3 Vhys Schmitt trigger voltage hysteresis 1) 2V VOL Output low level voltage 2) VDD=5V IIO=+2mA 400 mV RON Pull-up equivalent resistor 3) VIN=VSS VDD=5V 30 50 70 k Ω VDD=3V 90 1) tw(RSTL)out Generated reset pulse duration Internal reset sources 90 1) µs th(RSTL)in External reset pulse hold time 4) 20 µs tg(RSTL)in Filtered glitch duration 200 ns 1 |
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