SAP5SD-A-G1-R datasheet(22/67 Pages) RENESAS

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SAP51 / SAP5S Datasheet

January 28, 2016

Internal

EEPROM

Address

Bit Position

EEPROM Cell Contents

Description

Firmware Area

Synchronous_Data_IO

Synchronized Data I/O Mode

3 to 0

ID_Bit [3:0]

ID_Code

Inhibit_Write_ID1

ID_Code_Extension_1 is manufacturer configurable; refer to

section 5.20

3 to 0

ID2_Bit [3:0]

ID_Code_Extension_2

P1_Delay_Activation

If flag is set, the logic value at the parameter pin P1

determines whether the Delay_Mode function is active or

inactive; refer to Table 5.11

3 to 0

IO_Bit [3:0]

IO_Code

Lock_EE_PRG

Programming of the EEPROM Firmware region is possible

as long as this flag is not set (logic LOW).

Delay_Mode

Activates the Delay_Mode function, refer to Table 5.11

Invert_Data_In

All Data Port inputs are inverted.

Inhibit_BR01

If flag is set, the master call BR01 is not executed.

Inhibit_Watchdog

If flag is set, the watchdog is not activated.

P2_Sync_Activation

The Synchronized Data I/O Mode can be activated by

parameter bit P2 as described in Table 5.12.

Ext_Addr_4I/4O_Mode

4 Input/ 4 Output Mode in Extended Address Mode

Parallel_Out_4I/4O

Enables the parallel data output option in Extended Address

4I/4O Mode

Master_Mode

Master / Repeater Mode Flag

P0_Watchdog_Activation

The watchdog can be enabled / disabled by the logic value at

the parameter pin P0

4 to 0

Analog circuitry trim information

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