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SAP5SD-B-G1-R Scheda tecnica(PDF) 28 Page - Renesas Technology Corp

Il numero della parte SAP5SD-B-G1-R
Spiegazioni elettronici  AS-Interface Spec. V3.0 Compliant Universal AS-i IC
PDF  67 Pages
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Produttore elettronici  RENESAS [Renesas Technology Corp]
Homepage  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SAP5SD-B-G1-R Scheda tecnica(HTML) 28 Page - Renesas Technology Corp

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SAP51 / SAP5S Datasheet
© 2016 Integrated Device Technology, Inc.
28
January 28, 2016
5.2.
Thermal Protection
The SAP5 continuously monitors its silicon die temperature. If the temperature rises above approximately 140°C
for more than 2 seconds, the SAP5 will cut off the UOUT output from the internal voltage reference. Thus the
current consumption of the SAP5 will drop down to its operating current (refer to Table 2.2). In order to prevent an
undesired drawing of transmitter current, the transmitter is also disabled if the over-temperature cut off condition
occurs.
After an over-temperature cut-off, if the die temperature has cooled down by 10 to 20°C, the output voltage at
UOUT will be restored and the SAP5 performs an initialization with an additional time delay of 1s.
Table 5.4
Cut-Off Temperature
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNIT
Chip temperature for over-temperature shut down
TCutOff
125
160
°C
5.3.
DC Characteristics – Digital Inputs
The following pins contain digital high-voltage input stages:
Input-only pin:
PFAULT
I/O pins:
P1, P3, D1, D3, DSTBn, PSTBn, LED1 (PSTBn and LED1 are inputs for test purposes only)
3-level I/O pins:
P0, P2, D0, D2 (see table notes
1) and 2) in Table 5.5)
Table 5.5
DC Characteristics of Digital High Voltage Input Pins
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNIT
Voltage range for input “offset_low” level
1), 2)
VOFL
0
1.0
V
Voltage range for input “offset_high” level
1), 2)
VOFH
1.6
VUOUT
V
Voltage range for input “low” level
2)
VIL2
0
2.5
V
Voltage range for input “high” level
VIH
3.5
VUOUT
V
Current range for input “low” level
3)
IIL
VIN = 1V
-12
-3
µA
Current range for input “high” level
IIH
V0 ≥ VU5R
-10
10
µA
Capacitance at pin DSTBn
4)
CDL
10
pF
1)
The P0, P2, D0, D2 pins are used as 3-level inputs, i.e. inputs with offset detection, in Safety Mode only; otherwise configuration
depends on the slave profile. Refer to Table 5.15.
2)
The 3-level input pads contain independent comparators for the detection of regular input data level and offset. Refer to Figure 5.8
for constraints to the externally applied voltages in Safety Mode.
3)
The pull-up current is driven by a current source connected to U5R. It stays almost constant for input voltages ranging from 0 to
3.8V.
4)
The internal pull-up current is sufficient to avoid accidental triggering of an SAP5 reset if the DSTBn pin remains unconnected. For
external loads at DSTBn, a sufficient pull-up resistor is required to ensure VIH ≥ 3.5V in less than 90ms after the beginning of a
DSTBn = low pulse.



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