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DIO2240CMP8 Scheda tecnica(PDF) 8 Page - DIOO MICROCIRCUITS CO., LTD |
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DIO2240CMP8 Scheda tecnica(HTML) 8 Page - DIOO MICROCIRCUITS CO., LTD |
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8 / 24 page ![]() DIO2240 Version 1.2, Jan 2026 www.dioo.com © 2026 Dioo Microcircuits Co., Ltd. Jiangsu 4 Note: (1) RTI = Referred to input. (2) Guaranteed by design. (3) Specifications subject to change without notice. Output G Gain DIO2240E 10 V/V DIO2240A 20 DIO2240B 50 DIO2240C 100 DIO2240D 200 Gain error GND + 50 mV ≤ VOUT ≤ VS - 200 mV ±0.05 ±0.2 % Nonlinearity error (2) GND + 10 mV ≤ VOUT ≤ VS - 200 mV ±0.01 % RDA Reference divider accuracy All gains, VOUT = |(VREF1 – VREF2)| / 2 at VSENSE = 0 mV 0.02 % RVRR Reference voltage rejection ratio, RTI (1) DIO2240A, DIO2240B, 5 µV/V DIO2240E 15 Maximum capacitive load No sustained oscillation 1 nF Voltage output Swing to VS power-supply rail RL = 10 kΩ to VS/2 VS -0.15 VS -0.05 V Swing to GND RL = 10 kΩ to VS/2, VSENSE = 0 mV VREF1 = VREF2 = 0 V VGND +5 200 mV Frequency response BW Bandwidth -3 dB bandwidth DIO2240A 400 kHz DIO2240B 360 DIO2240E 800 tS Settling time output settles to 0.5% of final value DIO2240A 4 µs DIO2240B 7 DIO2240E 3 SR Slew rate 2.5 V/µs Noise, RTI (1) Voltage noise density 50 nV/√Hz |
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