EM78F651NAPSSLASHNAPJ datasheet(21/58 Pages) EMC

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EM78F651N

8-Bit Microcontroller

Product Specification (V1.1) 10.20.2006

• 17

(This specification is subject to change without further notice)

Individual interrupt is enabled by setting its associated control bit in the IOCF to "1".

Global interrupt is enabled by the ENI instruction and is disabled by the DISI instruction.

Refer to Fig 6-8.

The IOCF register is both readable and writable.

6.3 TCC/WDT & Prescaler

There are two 8-bit counters available as prescalers for the TCC and WDT respectively.

The PST0~PST2 bits of the CONT register are used to determine the ratio of the

prescaler of TCC. Likewise, the PSW0~PSW2 bits of the IOCE0 register are used to

determine the WDT prescaler. The prescaler counter will be cleared by the

instructions each time they are written into TCC. The WDT and prescaler will be

cleared by the “WDTC” and “SLEP” instructions. Fig 6-3 depicts the circuit diagram

of TCC/WDT.

R1 (TCC) is an 8-bit timer/counter. The clock source of TCC can be internal clock or

external signal input (edge selectable from the TCC pin). If TCC signal source is from

the internal clock, TCC will be incremented by 1 at every instruction cycle (without

prescaler). As illustrated in Fig 6-3, selection of CLK=Fosc/2 or CLK=Fosc/4

depends on the Code Option bit <CLKS>. CLK=Fosc/2 is selected if the CLKS bit is

"0", and CLK=Fosc/4 is selected if the CLKS bit is "1". If TCC signal source is from

external clock input, TCC will be incremented by 1 at every falling edge or rising edge

of the TCC pin. TCC pin input time length (kept in High or low level) must be greater

than 1CLK. The TCC will stop running when sleep mode occurs.

The watchdog timer is a free running on-chip RC oscillator. The WDT will keep on

running even after the oscillator driver has been turned off (i.e. in sleep mode).

During normal operation or sleep mode, a WDT time-out (if enabled) will cause the

device to reset. The WDT can be enabled or disabled at any time during normal

mode by software programming. Refer to WDTE bit of IOCE0 register. With no

prescaler, the WDT time-out period is approximately 18 ms

1 (one oscillator start-up

timer period).

It is recommended to use Port 6 Input Status Change Interrupt if user wants to

use the Interrupt function.

1 Note: VDD=5V, WDT time-out period = 16.5ms ± 8% VDD=3V

WDT time-out period = 18ms ± 8%.

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