EM78F651NAPSSLASHNAPJ datasheet(33/58 Pages) EMC

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EM78F651N

8-Bit Microcontroller

Product Specification (V1.1) 10.20.2006

• 29

(This specification is subject to change without further notice)

6.6 Interrupt

The EM78F651N, has three falling-edge interrupts listed below:

(1) TCC overflow interrupt

(2) Port 6 Input Status Change interrupt

(3) External interrupt [(P60, /INT) pin]

(4) LVD (Low Voltage Detector) interrupt

RF is the interrupt status register that records the interrupt requests in the relative

flags/bits. IOCF is the interrupt mask register. The global interrupt is enabled by the

ENI instruction and is disabled by the DISI instruction. When one of the enabled

interrupts occurs, the next instruction will be fetched from address in the priority as

shown in Table 10. Once in the interrupt service routine, the source of an interrupt

can be determined by polling the flag bits in RF. The interrupt flag bit must be

cleared by instructions before leaving the interrupt service routine and before

interrupts are enabled to avoid recursive interrupts.

When an interrupt is generated by the LVD (low voltage detector), in the code option

enable LVD interrupt is selected, the next instruction will be fetched from address

00CH.

When an interrupt is generated by the Timer clock/counter (if enabled), the next

instruction will be fetched from address 009 (TCC).

Before the Port 6 Input Status Change Interrupt is enabled, reading Port 6 (e.g. "MOV

R6,R6") is necessary. Each Port 6 pin will have this feature if its status changes.

The Port 6 Input Status Change Interrupt will wake up the EM78F651N from sleep

mode if it is enabled prior to going into sleep mode by executing SLEP instruction.

When wake-up occurs, the controller will continue to execute program in-line if the

global interrupt is disabled. If the global interrupt is enabled, it will branch out to the

interrupt vector 006H.

External interrupt equipped with digital noise rejection circuit (input pulse less than 8

system clocks time is eliminated as noise), but in Low crystal oscillator (LXT)

mode the noise rejection circuit will be disabled. When an interrupt (Falling edge)

is generated by the External interrupt (when enabled), the next instruction will be

fetched from address 003H.

The flag (except ICIF bit) in the Interrupt Status Register (RF) is set regardless of the

status of its mask bit or the execution of ENI. Note that the outcome of RF will be the

logic AND of RF and IOCF (refer to Fig 6-8). The RETI instruction ends the interrupt

routine and enables the global interrupt (the execution of ENI).

Before the interrupt subroutine is executed, the contents of ACC and the R3 and R4

R4 will be replaced by the new interrupt. After the interrupt service routine is finished,

ACC, R3 and R4 will be pushed back.

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